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(On-Board Computer (OBC))
(On-Board Computer (OBC))
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* with the mass spectrometer through a SPI link
 
* with the mass spectrometer through a SPI link
 
* with the GPS board through a SPI link
 
* with the GPS board through a SPI link
 +
 +
The data processing is distributed between a microprocessor and a FPGA logic.
 +
Additionally, a [[OBC/PIC PIC microcontroller]] bridges the FPGA to the [[OBC/CAN|OBC/CAN bus]].
  
 
= Attitude Determination and Control System (ADCS) =
 
= Attitude Determination and Control System (ADCS) =

Revision as of 10:59, 18 September 2020

Contents

CHESS mission

The CHESS mission wants to fly 2 Cubesats with primary mission to measure the earth’s atmosphere with the help of a mass spectrometer.

On-Board Computer (OBC)

The On-Board Computer (OBC) transfers information between the subsystems, mainly from the radio to mission payload and back.

In the CHESS mission, it communicates:

  • with the EPS through OBC/CAN
  • with the ADCS through a serial link
  • with the radios through a SPI link
  • with the mass spectrometer through a SPI link
  • with the GPS board through a SPI link

The data processing is distributed between a microprocessor and a FPGA logic. Additionally, a OBC/PIC PIC microcontroller bridges the FPGA to the OBC/CAN bus.

Attitude Determination and Control System (ADCS)

PIC18LF26K83

Configuration

Clock is set to the highest value (64MHz) as the board is made for test purposes. It could be lowered if a such speed is not needed for the final use. Typically in order to reduce power consumption

Note that if done so, some parameters may need to be changed

CAN

As described in the ADCS control document, the CAN configuration is the following : version 2.0 B, extended ID, SP set to 87.5% and SJW = 1, bus speed 125 kbps.

Register Hex Parameter Description
BRGCON1 0x0F BRP (2x16)/FOSC
SJW 1 x TQ
BRGCON2 0xBC PRSEG 5 x TQ
SAM once at sample point
SEG1PH 8 x TQ
SEG2PHTS Freely programmable
BRGCON3 0x01 SEG2PH 2 x TQ
WAKDIS Enable CAN wake-up
WAKFIL CAN line filter not used

UART

SPI

ADC

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