Synchro

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(Components)
(Components)
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* an assembly of a DC motor and an AC generator
 
* an assembly of a DC motor and an AC generator
 
* an [[Synchro#FPGA_board|FPGA prototyping board]]
 
* an [[Synchro#FPGA_board|FPGA prototyping board]]
* a [http://wiki.hevs.ch/uit/index.php5/Hardware/Parallelport/heb_synchro HEB Synchro] I/O board with 2 sinewave inputs and a PWM output
+
* an [[Synchro#Synchro_I.2FO_board|I/O board]] with 2 sinewave inputs and a PWM output
  
 
=== Motor-generator assembly ===
 
=== Motor-generator assembly ===
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=== Synchro I/O board ===
 
=== Synchro I/O board ===
  
The I/O board receives 2 sinewaves: one from a 50 Hz function generator and one from the AC generator.
+
The [http://wiki.hevs.ch/uit/index.php5/Hardware/Parallelport/heb_synchro HEB-synchro] I/O board receives 2 sinewaves: one from a 50 Hz function generator and one from the AC generator.
 
These signals are triggered at 0 V in order to deliver logic-levels signals to the FPGA.
 
These signals are triggered at 0 V in order to deliver logic-levels signals to the FPGA.
  

Revision as of 15:42, 16 January 2015

Contents

The Filière Energie et Techniques environnementales (FET) has the digital systems course and labs in the 3rd (autumn) semester. The semester counts 15 weeks and ends with a little project.

The aim to the project is to synchronise an AC motor used as a generator to a reference 50 HZ signal.

Specification

Function

The reference signal and the generator output are digitized to 1 bit with the help of two comparators. The digital circuit receives these signals and controls a DC motor coupled to the generator.

Circuit

The circuit works as follows:

  • the difference between the mains period and the generator period is calculated
  • if the generator is too slow, the DC motor voltage is raised; if the generator is too fast, the DC motor voltage is diminished

Components

The system consists of

Motor-generator assembly

The DC motor is controlled via a 12 V PWM signal. It is mechanically coupled to the DC generator. With a mean voltage of 6 V, the assembly turns at about 50 Hz.

FPGA board

The main board is the school's FPGA-EBS lab development board. It hosts a Xilinx Spartan xc3s500e FPGA and features many different interfaces.

Synchro I/O board

The HEB-synchro I/O board receives 2 sinewaves: one from a 50 Hz function generator and one from the AC generator. These signals are triggered at 0 V in order to deliver logic-levels signals to the FPGA.

The FPGA delivers a PWM output which controls a power switch. The switch then drives the DC motor.

Getting started

In order to start the projects you should do the following:

  • Read carefully the specifications above
  • Draw the architecture of the circuit in the form of a block diagram
  • Consult the guides for the first steps into the design software

Semester organization

Week schedule

Week Course Lab
1 NUM / COM PHA - phase accuracy display
(introduction to the tools)
2 COM / KAR NUM - numbers and operations
3 KAR / MUX ADD - binary adder
4 MUX / LST MUL - multiplier
5 LST / LAT PHD - phase detector
6 LAT PHD
7 CNT PHU - phase unwrapper
8 FSM COM - Serial port receiver
9 - 15 project

Additional Information

Additional informations for teachers.

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