Search results

Jump to: navigation, search
  • Showing below up to 20 results starting with #1.
Advanced search

Search in namespaces:

  
  
  
  
  
  
  
  
 

Page title matches

  • This board will be the master board on the [[HiRel/CanSat|CanSat system]]. ! Type || CanSat Master FPGA || Schematic || UCF || Description
    6 KB (730 words) - 15:22, 19 February 2018

Page text matches

  • == Master == [[Category:Bachelor]] [[Category:Master]]
    2 KB (246 words) - 12:17, 16 August 2021
  • The master also reads data values from the slave boards, stores them into a second set ...[[Kart/Bluetooth|Bluetooth RS232 modem]] sits on the [[Kart/FPGA board|I2C master FPGA]]
    7 KB (1,162 words) - 08:30, 3 September 2021
  • [[Category:Master]] [[Category:HiRel]] [[Category:CanSat]]
    2 KB (283 words) - 14:03, 24 April 2019
  • The I2C master has to acknowledge all data bytes (FF) except for the last one.
    427 B (69 words) - 09:06, 25 July 2014
  • When reading multiple bytes, the master has to pull <code>ACK</code> low between the <code>FF</code><sub>h</sub> wo
    4 KB (627 words) - 09:26, 19 August 2021
  • This board will be the master board on the [[HiRel/CanSat|CanSat system]]. ! Type || CanSat Master FPGA || Schematic || UCF || Description
    6 KB (730 words) - 15:22, 19 February 2018
  • On the DC motor master solution :
    2 KB (267 words) - 11:32, 19 August 2021
  • The protocol consists of a repeated polling. At a rate of 1 kHz, the I2C master:
    3 KB (377 words) - 08:14, 19 August 2016
  • ...r Bus Architecture (AMBA)]. Sein spezielles Merkmal ist, dass er nur einen Master zulässt. In einem Peripheriebaustein müssen die Werte, welche der Master (hier Mikroprozessor) in die Register schreibt, gespeichert werden.
    2 KB (323 words) - 12:55, 17 April 2015
  • ...r Bus Architecture (AMBA)]. Sein spezielles Merkmal ist, dass er nur einen Master zulässt. In einem Peripheriebaustein müssen die Werte, welche der Master (hier Mikroprozessor) in die Register schreibt, gespeichert werden.
    3 KB (350 words) - 08:44, 9 March 2021
  • ...wird durch die serielle Schnittstelle '''ahbuart''' gesteuert, welches ein Master des AMBA Busses ist.
    5 KB (677 words) - 21:10, 19 June 2013
  • == Master data ==
    6 KB (882 words) - 14:22, 26 August 2021
  • The FPGA board serves as master (or as a router) and therefore connects to all other boards through 4 doubl Each one of the four 6 pin connectors on the master board connect to exactly one slave board.
    3 KB (482 words) - 08:07, 19 June 2018
  • AHB-Lite est un sous-ensemble simplifié avec un seul master ([[Media:AMBA_AHB-Lite_spec.pdf|Specification]]).
    2 KB (321 words) - 09:04, 14 April 2015
  • Modify the master version of the project on <code>[https://repos.hevs.ch/svn/eda/VHDL/labs/Au
    3 KB (499 words) - 16:11, 29 January 2020
  • [[Category:Master]] [[Category:HiRel]] [[Category:CanSat]]
    3 KB (435 words) - 11:08, 2 May 2017
  • [[Category:Master]] [[Category:HiRel]] [[Category:CanSat]]
    3 KB (504 words) - 09:48, 1 June 2016
  • [[Category:Master]] [[Category:HiRel]] [[Category:CanSat]]
    3 KB (486 words) - 14:22, 5 April 2017
  • [[Category:Master]] [[Category:HiRel]] [[Category:CanSat]]
    3 KB (422 words) - 11:37, 29 May 2015
  • the default views are changed and the master solution is removed. Commit all changes after having worked on the master repository:
    7 KB (1,134 words) - 10:50, 23 November 2020

View (previous 20 | next 20) (20 | 50 | 100 | 250 | 500)

Personal tools
Namespaces
Variants
Views
Actions
Navigation
Modules / Projects
Browse
Toolbox