HiRel/CanSat/Master FPGA

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{{TOC right}}
 
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This board will be the master board on the [[HiRel/CanSat]].
 
This board will be the master board on the [[HiRel/CanSat]].
  
= Design =
+
= System =
  
The design will hold a soft-core microprocessor controlling the different slaves on the [[HiRel/CanSat]]
+
The design contains a soft-core processor controlling the different slaves of the [[HiRel/CanSat]]
via peripheral devices attached to an
+
via peripheral devices attached to it by an
 
[http://en.wikipedia.org/wiki/Advanced_Microcontroller_Bus_Architecture#Advanced_High-performance_Bus_.28AHB.29 AHB-lite] bus system.
 
[http://en.wikipedia.org/wiki/Advanced_Microcontroller_Bus_Architecture#Advanced_High-performance_Bus_.28AHB.29 AHB-lite] bus system.
  
== Complexity Estimation ==
+
== Connections ==
  
A basic design used in earlier runs of the HiRel course serves as base for the estimation of the needed FPGA resources.
+
The FPGA board connectors consist of 4 dual [http://en.wikipedia.org/wiki/Pmod_Interface Pmods], each having 12 pins.
 +
The Pmods are connected to the slave boards via the bottom and the top ring.
 +
 
 +
= FPGA comparisons =
 +
 
 +
The choice of the FPGA was based on a comparison of synthesis results of a simple AHB-Lite system.
  
 
{|class=wikitable
 
{|class=wikitable
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| Microsemi    || AGL60  || 16.4                || 56896        || 3704          || 2          || 4
 
| Microsemi    || AGL60  || 16.4                || 56896        || 3704          || 2          || 4
 
|-
 
|-
| Microsemi    || AGL250  || 75.3                || 807          || 13            || 4          || 32
+
| Microsemi    || AGL250  || || || || ||
 
|}
 
|}
  
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On the other hand the Xilinx Spartan 6 FPGAs are quite spacious, immediately available and have a reasonable price (<20$).
 
On the other hand the Xilinx Spartan 6 FPGAs are quite spacious, immediately available and have a reasonable price (<20$).
 
Furthermore we already use them successfully on our [http://wiki.hevs.ch/uit/index.php5/Hardware/FPGARack FPGArack] board.
 
Furthermore we already use them successfully on our [http://wiki.hevs.ch/uit/index.php5/Hardware/FPGARack FPGArack] board.
 
= Component =
 
 
[TBC]
 
  
 
[[Category:Master]] [[Category:HiRel]] [[Category:CanSat]]
 
[[Category:Master]] [[Category:HiRel]] [[Category:CanSat]]

Revision as of 13:03, 12 January 2015

Contents

This board will be the master board on the HiRel/CanSat.

System

The design contains a soft-core processor controlling the different slaves of the HiRel/CanSat via peripheral devices attached to it by an AHB-lite bus system.

Connections

The FPGA board connectors consist of 4 dual Pmods, each having 12 pins. The Pmods are connected to the slave boards via the bottom and the top ring.

FPGA comparisons

The choice of the FPGA was based on a comparison of synthesis results of a simple AHB-Lite system.

Manufacturer Device Estimated Frequency LUTs / CoreCells Memory
[MHz]  % Needed Available
Xilinx XC6SLX9 75.3 807 13 4 32
Microsemi AGL60 16.4 56896 3704 2 4
Microsemi AGL250

As it is visible in the table above, the smaller Microsemi Igloo devices are too small for us. Bigger Microsemi Igloo devices however are not easily available and also quite expensive (>80$). On the other hand the Xilinx Spartan 6 FPGAs are quite spacious, immediately available and have a reasonable price (<20$). Furthermore we already use them successfully on our FPGArack board.

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