HiRel/CanSat/Master FPGA

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The Pmods are connected to the slave boards via the bottom and the top ring.
 
The Pmods are connected to the slave boards via the bottom and the top ring.
  
−
{|class=wikitable
+
{|class=wikitable style="margin: 0 auto"
 
|-
 
|-
−
! connector || board || Signal || Pmod pin || FPGA pin
+
! board || connector || Signal || Pmod pin || FPGA pin
 
|-
 
|-
−
<!-- S1 bottom, Power board -->
+
<!-- slave 1, power board, bottom -->
−
| rowspan=4 | S1 bottom || rowspan=4 | power || TxD || J1.1 || 127
+
| rowspan=8 | slave 1:<br />[[HiRel/CanSat/Slave_Power|power supply]] || rowspan=4 | bottom || TxD || J2.1 || 14
 
|-
 
|-
−
| RxD || J1.3 || 124
+
| RxD || J2.3 || 11
 
|-
 
|-
−
| LED 0 || J1.5 || 121
+
| LED 0 || J2.5 || 8
 
|-
 
|-
−
| LED 1 || J1.7 || 118
+
| LED 1 || J2.7 || 5
 
|-
 
|-
−
<!-- S2 bottom , COM board -->
+
<!-- slave 1, power board, top -->
−
| rowspan=4 | S2 bottom || rowspan=4 | Computer On Module || RxD1 || J1.2 || 126
+
| rowspan=4 | top || switch 0 || J4.1 || 24
 
|-
 
|-
−
| TxD1 || J1.4 || 123
+
| switch 1 || J4.3 || 27
 
|-
 
|-
−
| GPIO 168 || J1.6 || 119
+
| switch 2 || J4.5 || 32
 
|-
 
|-
−
| GPIO 167 || J1.8 || 117
+
| switch 3 || J4.7 || 35
 
|-
 
|-
−
<!-- S3 bottom, Sensor board -->
+
<!-- slave 2, XBee Board, bottom -->
−
| rowspan=4 | S1 bottom || rowspan=4 | sensors || CS_n || J1.1 || 127
+
| rowspan=8 | slave 2:<br />[[HiRel/CanSat/Slave_XBee|XBee radio]] || rowspan=4 | bottom || RxD || J2.2 || 15
 
|-
 
|-
−
| MOSI || J1.3 || 124
+
| TxD || J2.4 || 12
 
|-
 
|-
−
| MISO || J1.5 || 121
+
| reset || J2.6 || 9
 
|-
 
|-
−
| SClk || J1.7 || 118
+
| sleep request || J2.8 || 6
 
|-
 
|-
−
<!-- S4 bottom , XBee Board -->
+
<!-- slave 2, XBee board, top -->
−
| rowspan=4 | S2 bottom || rowspan=4 | XBee radio || RxD || J1.2 || 126
+
| rowspan=4 | top || RSSI PWM || J4.2 || 23
 
|-
 
|-
−
| TxD1 || J1.4 || 123
+
| associate || J4.4 || 26
 
|-
 
|-
−
| reset || J1.6 || 119
+
| DIO || J4.6 || 30
 
|-
 
|-
−
| sleep request || J1.8 || 117
+
| sleep || J4.8 || 33
 
|-
 
|-
−
<!-- S1 top, COM board -->
+
<!-- slave 3, COM board, bottom -->
−
| S1 top || Computer On Module || colspan=3 | audio signals
+
| rowspan=5 | slave 3:<br />[[HiRel/CanSat/Slave_Gumstix|Computer On Module]] || rowspan=4 | bottom || RxD1 || J1.1 || 126
 
|-
 
|-
−
<!-- S2 top, Power board -->
+
| TxD1 || J1.3 || 123
−
| rowspan=4 | S2 top || rowspan=4 | power || switch 0 || J3.2 || 133
+
 
|-
 
|-
−
| switch 1 || J3.4 || 137
+
| GPIO 168 || J1.5 || 119
 
|-
 
|-
−
| switch 2 || J3.6 || 139
+
| GPIO 167 || J1.7 || 117
 
|-
 
|-
−
| switch 3 || J3.8 || 141
+
<!-- slave 3, COM board, top -->
 +
| top || colspan=3 | audio signals
 
|-
 
|-
−
<!-- S3 top, XBee board -->
+
<!-- slave 4, Sensor board, bottom -->
−
| rowspan=4 | S2 top || rowspan=4 | XBee radio || RSSI PWM || J3.1 || 133
+
| rowspan=6 | slave 4:<br />[[HiRel/CanSat/Slave_Sensors|sensors]] || rowspan=4 | bottom || CS_n || J1.2 || 126
 
|-
 
|-
−
| associate || J3.3 || 137
+
| MOSI || J1.4 || 123
 
|-
 
|-
−
| DIO || J3.5 || 139
+
| MISO || J1.6 || 119
 
|-
 
|-
−
| sleep || J3.7 || 141
+
| SClk || J1.8 || 117
 
|-
 
|-
−
<!-- S4 top, sensor board -->
+
<!-- slave 4, sensor board, top -->
−
| rowspan=4 | S2 top || rowspan=4 | sensors || int_n || J3.1 || 133
+
| rowspan=4 | top || int_n || J3.2 || 133
 
|-
 
|-
−
| cnvt_n || J3.7 || 141
+
| cnvt_n || J3.8 || 141
 
|-
 
|-
 
|}
 
|}

Revision as of 18:54, 12 January 2015

Contents

This board will be the master board on the HiRel/CanSat.

System

The design contains a soft-core processor controlling the different slaves of the HiRel/CanSat via peripheral devices attached to it by an AHB-lite bus system.

Connections

The FPGA board connectors consist of 4 dual Pmods, each having 12 pins. The Pmods are connected to the slave boards via the bottom and the top ring.

board connector Signal Pmod pin FPGA pin
slave 1:
power supply 		bottom TxD J2.1 14
RxD J2.3 11
LED 0 J2.5 8
LED 1 J2.7 5
top switch 0 J4.1 24
switch 1 J4.3 27
switch 2 J4.5 32
switch 3 J4.7 35
slave 2:
XBee radio 		bottom RxD J2.2 15
TxD J2.4 12
reset J2.6 9
sleep request J2.8 6
top RSSI PWM J4.2 23
associate J4.4 26
DIO J4.6 30
sleep J4.8 33
slave 3:
Computer On Module 		bottom RxD1 J1.1 126
TxD1 J1.3 123
GPIO 168 J1.5 119
GPIO 167 J1.7 117
top audio signals
slave 4:
sensors 		bottom CS_n J1.2 126
MOSI J1.4 123
MISO J1.6 119
SClk J1.8 117
top int_n J3.2 133
cnvt_n J3.8 141

FPGA comparisons

The choice of the FPGA was based on a comparison of synthesis results of a simple AHB-Lite system.

Manufacturer Device Estimated Frequency LUTs / CoreCells Memory
[MHz]  % Needed Available
Xilinx XC6SLX9 75.3 807 13 4 32
Microsemi AGL60 16.4 56896 3704 2 4
Microsemi AGL250

As it is visible in the table above, the smaller Microsemi Igloo devices are too small for us. Bigger Microsemi Igloo devices however are not easily available and also quite expensive (>80$). On the other hand the Xilinx Spartan 6 FPGAs are quite spacious, immediately available and have a reasonable price (<20$). Furthermore we already use them successfully on our FPGArack board.

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