HiRel/CanSat/Master FPGA

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(FPGA comparisons)
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! Manufacturer || Device  || Estimated Frequency || colspan="2" | LUTs / CoreCells || colspan="2" | Memory
 
! Manufacturer || Device  || Estimated Frequency || colspan="2" | LUTs / CoreCells || colspan="2" | Memory
 
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|             ||        || [MHz]              ||              ||            % || Needed      || Available
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!             ||        || [MHz]              ||              ||            % || Needed      || Available
 
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| Xilinx      || XC6SLX9 || 75.3                || 807          || 13            || 4          || 32
 
| Xilinx      || XC6SLX9 || 75.3                || 807          || 13            || 4          || 32

Revision as of 13:38, 23 January 2015

Contents

This board will be the master board on the HiRel/CanSat.

System

The design contains a soft-core processor controlling the different slaves of the HiRel/CanSat via peripheral devices attached to it by an AHB-lite bus system.

Connections

The FPGA board hosts a 106.25 MHz oscillator and a button which can be used as a reset signal.

Signal FPGA pin FPGA dir
clock 16 in
reset_n 2 in

The FPGA board connectors consist of 4 dual Pmods, each having 12 pins. The Pmods are connected to the slave boards via the bottom and the top ring.

board connector Signal Pmod pin FPGA pin FPGA dir
slave 1:
power supply
bottom TxD J2.1 14 127
RxD J2.3 11 124
LED 0 J2.5 8 121 out
LED 1 J2.7 5 118 out
top switch 0 J4.1 24 134 in
switch 1 J4.3 27 138 in
switch 2 J4.5 32 140 in
switch 3 J4.7 35 142 in
slave 2:
XBee radio
bottom RxD J2.2 15 126
TxD J2.4 12 123
reset J2.6 9 119
sleep request J2.8 6 117
top RSSI PWM J4.2 23 133
associate J4.4 26 137
DIO J4.6 30 139
sleep J4.8 33 141
slave 3:
Computer On Module
bottom RxD1 J1.1 126 14
TxD1 J1.3 123 11
GPIO 168 J1.5 119 8
GPIO 167 J1.7 117 5
top HSOLF J3.2 24
HSORF J3.4 27
AUXRF J3.6 32
AUXLF J3.8 35
slave 4:
sensors
bottom CS_n J1.2 126 15 out
MOSI J1.4 123 12 out
MISO J1.6 119 9 in
SClk J1.8 117 6 out
top int_n J3.2 133 23
J3.4 26
J3.6 30
cnvt_n J3.8 141 33

FPGA comparisons

The choice of the FPGA was based on a comparison of synthesis results of a simple AHB-Lite system.

Manufacturer Device Estimated Frequency LUTs / CoreCells Memory
[MHz]  % Needed Available
Xilinx XC6SLX9 75.3 807 13 4 32
Microsemi AGL60 16.4 56896 3704 2 4
Microsemi AGL250

As it is visible in the table above, the smaller Microsemi Igloo devices are too small for us. Bigger Microsemi Igloo devices however are not easily available and also quite expensive (>80$). On the other hand the Xilinx Spartan 6 FPGAs are quite spacious, immediately available and have a reasonable price (<20$). Furthermore we already use them successfully on our FPGArack board.

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