Libero IDE presentation

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we laucnch [https://www.microsemi.com/product-directory/design-resources/1751-libero-ide Libero IDE]
 
we laucnch [https://www.microsemi.com/product-directory/design-resources/1751-libero-ide Libero IDE]
 
directly from [https://www.mentor.com/products/fpga/hdl_design/hdl_designer_series/ HDL Designer].
 
directly from [https://www.mentor.com/products/fpga/hdl_design/hdl_designer_series/ HDL Designer].
* the <code>prepare for synthesis</code> task does the following:
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=== Files ===
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The necessary design files are in <code>$PATH/Board/Libero</code>.
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They consist of:
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$DESIGN.prjx
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synthesis/$DESIGN_syn.prj
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designer/impl1/$DESIGN.adb
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designer/impl1/$DESIGN.ide_des
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designer/impl1/$DESIGN.pdb
 +
 
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These files are copied in a temporary directory which will be additionally populated by the numerous design files generated by the deign tool.
 +
 
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=== Tasks ===
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Launching the tools is done in two steps.
 +
* with the top-level block selected, the <code>prepare for synthesis</code> task does the following:
 
** the design tool generates a single VHDL file
 
** the design tool generates a single VHDL file
 
** the <code>trimLibs.pl</code> script replaces all library definitions with the one of <code>work</code>
 
** the <code>trimLibs.pl</code> script replaces all library definitions with the one of <code>work</code>

Revision as of 12:02, 21 December 2020

Contents

Libero IDE is used to program the Microchip FPGAs.

Work environment

At HEI, we laucnch Libero IDE directly from HDL Designer.

Files

The necessary design files are in $PATH/Board/Libero. They consist of:

$DESIGN.prjx
synthesis/$DESIGN_syn.prj
designer/impl1/$DESIGN.adb
designer/impl1/$DESIGN.ide_des
designer/impl1/$DESIGN.pdb

These files are copied in a temporary directory which will be additionally populated by the numerous design files generated by the deign tool.

Tasks

Launching the tools is done in two steps.

  • with the top-level block selected, the prepare for synthesis task does the following:
    • the design tool generates a single VHDL file
    • the trimLibs.pl script replaces all library definitions with the one of work
  • the Libero Project Navigator task does the following:
    • the Update prjx.pl script updates the paths specified in the .prjx file to reflect the project location's.
    • the Libero IDE is launched
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