Libero IDE presentation
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=== Files === | === Files === | ||
| − | The | + | The main design files are located in <code>$PATH/Board/concat</code>: |
| − | + | $DESIGN.vhd | |
| + | $DESIGN.pdc | ||
| + | |||
| + | The Physical Design Constraints <code>.pdc</code> file specifies the I/O locations and electric levels. | ||
| + | |||
| + | Further design files are found in <code>$PATH/Board/Libero</code>: | ||
$DESIGN.prjx | $DESIGN.prjx | ||
synthesis/$DESIGN_syn.prj | synthesis/$DESIGN_syn.prj | ||
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designer/impl1/$DESIGN.pdb | designer/impl1/$DESIGN.pdb | ||
| − | + | This second set of files is copied into a temporary directory which will be additionally populated by the numerous design files generated by the deign tool. | |
=== Tasks === | === Tasks === | ||
Revision as of 13:11, 21 December 2020
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Libero IDE is used to program the Microchip FPGAs.
Work environment
At HEI, we laucnch Libero IDE directly from HDL Designer.
Files
The main design files are located in $PATH/Board/concat:
$DESIGN.vhd $DESIGN.pdc
The Physical Design Constraints .pdc file specifies the I/O locations and electric levels.
Further design files are found in $PATH/Board/Libero:
$DESIGN.prjx synthesis/$DESIGN_syn.prj designer/impl1/$DESIGN.adb designer/impl1/$DESIGN.ide_des designer/impl1/$DESIGN.pdb
This second set of files is copied into a temporary directory which will be additionally populated by the numerous design files generated by the deign tool.
Tasks
Launching the tools is done in two steps.
- with the top-level block selected, the
prepare for synthesistask does the following:- the design tool generates a single VHDL file
- the
trimLibs.plscript replaces all library definitions with the one ofwork
- the
Libero Project Navigatortask does the following:- the
Update prjx.plscript updates the paths specified in the.prjxfile to reflect the project location's. - the Libero IDE is launched
- the
