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2024-03-29T10:23:03Z
User contributions
MediaWiki 1.18.1
https://wiki.hevs.ch/uit/index.php5/Hardware/FPGAPoetic
Hardware/FPGAPoetic
2022-07-12T13:50:08Z
<p>Tristan.renon: /* Analog to digital converters */</p>
<hr />
<div>{{TOC right}}<br />
<br />
The basic idea behind this board is to have a FPGA board that interface a VME connector compatible with the POETIC Rack backplane.<br />
This board was developped during [https://gitlab.hevs.ch/theses/bachelor/jean-nanchen/fpga-developing-board-demonstrator Jean Nanchen's TB] (2021) and used in the NGRW project in addition with the [[Hardware/Mezzanine/Poetic|FPGA ADC-DAC Mezzanine]].<br />
<br />
{|class=wikitable<br />
|-<br />
! Type || FPGA Poetic || Schematic || UCF || Description<br />
|-<br />
| V1.0 || [[File:FpgaPoetic.png|200px|FPGA Poetic V1.0]] || [[Media:FPGAPoetic_v1_0_schematics.pdf|FPGA-Poetic v1.0 Schematic PDF]] || [[Media:FPGARack_v1_0.ucf|FPGA-Rack v1.0 UCF Files]] || There are different FPGA mounted: Spartan 6 XC6SLX45, Spartan 6 XC6SLX100, Spartan 6 XC6SLX150<br />
|-<br />
|}<br />
<br />
<br />
= Features =<br />
* 1 Ethernet Port<br />
* USB FTDI<br />
* Spartan 6 LX45 - LX100 - LX150<br />
* 2x4 Leds<br />
* 4 User Switches<br />
* 3 Buttons<br />
* 100.0MHz Main Clock<br />
* VME connector 3x32Pin compatible with POETIC Rack backplane<br />
* 2 Mezzanine Connector ARM-EBS and FPGA-EBS compatible<br />
* Powered by USB or VME Power<br />
<br />
= Analog to digital converters =<br />
<br />
The mezzanine board holds 20 [https://www.ti.com/product/ADS7886 ADS7886] analog to digital converters.<br />
<br />
These are 12&nbsp;bit converters with a maximal sampling rate of 1&nbsp;MHz.<br />
<br />
<span style="color:red">Actually Channel 6, 7, 8, 9, 10, 12, 13, 14 and 15 don't work (Probably due to propagation delay with SCLK)</span><br />
<br />
= Digital to analog converters =<br />
<br />
The mezzanine board holds 2 [https://www.ti.com/product/DAC124S085 DAC124S085] quad analog to digital converters,<br />
allowing for 8 analog output channels.<br />
<br />
These are quad 12&nbsp;bit converters with a maximal sampling rate of 1.8&nbsp;MHz if only one channel is used.<br />
The sampling rate drops to 460&nbsp;kHz when all 4 channels are used.<br />
<br />
= Programmation =<br />
V1.0 is only programmable via JTAG.<br />
<br />
= Links =<br />
* [http://www.xilinx.com/support/documentation/spartan-6.htm Xilinx Spartan 6 Documents]<br />
* [[Standards/VME|VME Description]]<br />
<br />
<br />
[[Category:Hardware]] [[Category:FPGARack]]</div>
Tristan.renon
https://wiki.hevs.ch/uit/index.php5/Hardware/FPGAPoetic
Hardware/FPGAPoetic
2022-07-12T13:49:24Z
<p>Tristan.renon: /* Analog to digital converters */</p>
<hr />
<div>{{TOC right}}<br />
<br />
The basic idea behind this board is to have a FPGA board that interface a VME connector compatible with the POETIC Rack backplane.<br />
This board was developped during [https://gitlab.hevs.ch/theses/bachelor/jean-nanchen/fpga-developing-board-demonstrator Jean Nanchen's TB] (2021) and used in the NGRW project in addition with the [[Hardware/Mezzanine/Poetic|FPGA ADC-DAC Mezzanine]].<br />
<br />
{|class=wikitable<br />
|-<br />
! Type || FPGA Poetic || Schematic || UCF || Description<br />
|-<br />
| V1.0 || [[File:FpgaPoetic.png|200px|FPGA Poetic V1.0]] || [[Media:FPGAPoetic_v1_0_schematics.pdf|FPGA-Poetic v1.0 Schematic PDF]] || [[Media:FPGARack_v1_0.ucf|FPGA-Rack v1.0 UCF Files]] || There are different FPGA mounted: Spartan 6 XC6SLX45, Spartan 6 XC6SLX100, Spartan 6 XC6SLX150<br />
|-<br />
|}<br />
<br />
<br />
= Features =<br />
* 1 Ethernet Port<br />
* USB FTDI<br />
* Spartan 6 LX45 - LX100 - LX150<br />
* 2x4 Leds<br />
* 4 User Switches<br />
* 3 Buttons<br />
* 100.0MHz Main Clock<br />
* VME connector 3x32Pin compatible with POETIC Rack backplane<br />
* 2 Mezzanine Connector ARM-EBS and FPGA-EBS compatible<br />
* Powered by USB or VME Power<br />
<br />
= Analog to digital converters =<br />
<br />
The mezzanine board holds 20 [https://www.ti.com/product/ADS7886 ADS7886] analog to digital converters.<br />
<br />
These are 12&nbsp;bit converters with a maximal sampling rate of 1&nbsp;MHz.<br />
<br />
{{font color|red|Actually Channel 6, 7, 8, 9, 10, 12, 13, 14 and 15 don't work (Probably due to propagation delay with SCLK)}}<br />
<br />
= Digital to analog converters =<br />
<br />
The mezzanine board holds 2 [https://www.ti.com/product/DAC124S085 DAC124S085] quad analog to digital converters,<br />
allowing for 8 analog output channels.<br />
<br />
These are quad 12&nbsp;bit converters with a maximal sampling rate of 1.8&nbsp;MHz if only one channel is used.<br />
The sampling rate drops to 460&nbsp;kHz when all 4 channels are used.<br />
<br />
= Programmation =<br />
V1.0 is only programmable via JTAG.<br />
<br />
= Links =<br />
* [http://www.xilinx.com/support/documentation/spartan-6.htm Xilinx Spartan 6 Documents]<br />
* [[Standards/VME|VME Description]]<br />
<br />
<br />
[[Category:Hardware]] [[Category:FPGARack]]</div>
Tristan.renon
https://wiki.hevs.ch/uit/index.php5/Hardware/FPGAPoetic
Hardware/FPGAPoetic
2022-07-12T13:46:50Z
<p>Tristan.renon: /* Features */</p>
<hr />
<div>{{TOC right}}<br />
<br />
The basic idea behind this board is to have a FPGA board that interface a VME connector compatible with the POETIC Rack backplane.<br />
This board was developped during [https://gitlab.hevs.ch/theses/bachelor/jean-nanchen/fpga-developing-board-demonstrator Jean Nanchen's TB] (2021) and used in the NGRW project in addition with the [[Hardware/Mezzanine/Poetic|FPGA ADC-DAC Mezzanine]].<br />
<br />
{|class=wikitable<br />
|-<br />
! Type || FPGA Poetic || Schematic || UCF || Description<br />
|-<br />
| V1.0 || [[File:FpgaPoetic.png|200px|FPGA Poetic V1.0]] || [[Media:FPGAPoetic_v1_0_schematics.pdf|FPGA-Poetic v1.0 Schematic PDF]] || [[Media:FPGARack_v1_0.ucf|FPGA-Rack v1.0 UCF Files]] || There are different FPGA mounted: Spartan 6 XC6SLX45, Spartan 6 XC6SLX100, Spartan 6 XC6SLX150<br />
|-<br />
|}<br />
<br />
<br />
= Features =<br />
* 1 Ethernet Port<br />
* USB FTDI<br />
* Spartan 6 LX45 - LX100 - LX150<br />
* 2x4 Leds<br />
* 4 User Switches<br />
* 3 Buttons<br />
* 100.0MHz Main Clock<br />
* VME connector 3x32Pin compatible with POETIC Rack backplane<br />
* 2 Mezzanine Connector ARM-EBS and FPGA-EBS compatible<br />
* Powered by USB or VME Power<br />
<br />
= Analog to digital converters =<br />
<br />
The mezzanine board holds 20 [https://www.ti.com/product/ADS7886 ADS7886] analog to digital converters.<br />
<br />
These are 12&nbsp;bit converters with a maximal sampling rate of 1&nbsp;MHz.<br />
<br />
= Digital to analog converters =<br />
<br />
The mezzanine board holds 2 [https://www.ti.com/product/DAC124S085 DAC124S085] quad analog to digital converters,<br />
allowing for 8 analog output channels.<br />
<br />
These are quad 12&nbsp;bit converters with a maximal sampling rate of 1.8&nbsp;MHz if only one channel is used.<br />
The sampling rate drops to 460&nbsp;kHz when all 4 channels are used.<br />
<br />
= Programmation =<br />
V1.0 is only programmable via JTAG.<br />
<br />
= Links =<br />
* [http://www.xilinx.com/support/documentation/spartan-6.htm Xilinx Spartan 6 Documents]<br />
* [[Standards/VME|VME Description]]<br />
<br />
<br />
[[Category:Hardware]] [[Category:FPGARack]]</div>
Tristan.renon
https://wiki.hevs.ch/uit/index.php5/Hardware/FPGAPoetic
Hardware/FPGAPoetic
2021-10-01T12:01:25Z
<p>Tristan.renon: </p>
<hr />
<div>{{TOC right}}<br />
<br />
The basic idea behind this board is to have a FPGA board that interface a VME connector compatible with the POETIC Rack backplane.<br />
This board was developped during [https://gitlab.hevs.ch/theses/bachelor/jean-nanchen/fpga-developing-board-demonstrator Jean Nanchen's TB] (2021) and used in the NGRW project in addition with the [[Hardware/Mezzanine/Poetic|FPGA ADC-DAC Mezzanine]].<br />
<br />
{|class=wikitable<br />
|-<br />
! Type || FPGA Poetic || Schematic || UCF || Description<br />
|-<br />
| V1.0 || [[File:FpgaPoetic.png|200px|FPGA Poetic V1.0]] || [[Media:FPGAPoetic_v1_0_schematics.pdf|FPGA-Poetic v1.0 Schematic PDF]] || [[Media:FPGARack_v1_0.ucf|FPGA-Rack v1.0 UCF Files]] || There are different FPGA mounted: Spartan 6 XC6SLX45, Spartan 6 XC6SLX100, Spartan 6 XC6SLX150<br />
|-<br />
|}<br />
<br />
<br />
= Features =<br />
* 1 Ethernet Port<br />
* USB FTDI<br />
* Spartan 6 LX45 - LX100 - LX150<br />
* 2x4 Leds<br />
* 4 User Switches<br />
* 3 Buttons<br />
* 106.25MHz Main Clock<br />
* VME connector 3x32Pin compatible with POETIC Rack backplane<br />
* 2 Mezzanine Connector ARM-EBS and FPGA-EBS compatible<br />
* Powered by USB or VME Power<br />
<br />
= Programmation =<br />
V1.0 is only programmable via JTAG.<br />
<br />
= Links =<br />
* [http://www.xilinx.com/support/documentation/spartan-6.htm Xilinx Spartan 6 Documents]<br />
* [[Standards/VME|VME Description]]<br />
<br />
<br />
[[Category:Hardware]] [[Category:FPGARack]]</div>
Tristan.renon
https://wiki.hevs.ch/uit/index.php5/Hardware/Mezzanine/Poetic
Hardware/Mezzanine/Poetic
2021-10-01T12:00:43Z
<p>Tristan.renon: </p>
<hr />
<div>{{TOC right}}<br />
<br />
== 10 ADCs, 8 DACs ==<br />
<br />
This mezzanine was developped for the FPGA Poetic Board during [https://gitlab.hevs.ch/theses/bachelor/jean-nanchen/fpga-developing-board-demonstrator Jean Nanchen's TB] (2021) and used in the NGRW project with the [[Hardware/FPGAPoetic|FPGA Poetic Board]].<br />
The mezzanine board has 8 SMA connectors (DAC output), 2 connectors 2x10 pins (ADC input), 1 connector 2x5 pins (SPI LVDS) and 1 connector 2x9 pins (SPARE I/O).<br />
<br />
This board is used for the EMVS students project day.<br />
<br />
{|class=wikitable<br />
|- <br />
! Version || Photo || Schematic<br />
|-<br />
| V1.0 || [[File:Poetic Mezza ADC DAC.png|200px|ADC-DAC Mezzanine]] || [[Media:FPGA_Mezza_ADC_DAC_schematic.pdf|FPGA ADC DAC Mezza Schematic PDF]]<br />
|}<br />
<br />
=== ADCs ===<br />
The [https://www.ti.com/product/ADS7886 ADS7886] is a 6 12-Bit, 1-MSPS ADC.<br />
<br />
<br />
=== DACs ===<br />
The [https://www.ti.com/product/DAC084S085 DAC084S085] is a Quad 8-Bit DAC with a serial interface that is compatible with standard SPI,<br />
QSPI, MICROWIRE, and DSP interfaces.<br />
<br />
[[Category:Hardware]] [[Category:Mezzanine]]</div>
Tristan.renon
https://wiki.hevs.ch/uit/index.php5/Hardware/FPGAPoetic
Hardware/FPGAPoetic
2021-10-01T11:59:38Z
<p>Tristan.renon: </p>
<hr />
<div>{{TOC right}}<br />
<br />
The basic idea behind this board is to have a FPGA board that interface a VME connector compatible with the POETIC Rack backplane.<br />
This board was developped during [https://gitlab.hevs.ch/theses/bachelor/jean-nanchen/fpga-developing-board-demonstrator Jean Nanchen's TB] (2021) and used in the NGRW project in addition with the [[Hardware/Mezzanine/Poetic|FPGA ADC-DAC Mezzanine]].<br />
<br />
{|class=wikitable<br />
|-<br />
! Type || FPGA Poetic || Schematic || UCF || Description<br />
|-<br />
| V1.0 || [[File:FpgaPoetic.png|200px|FPGA Poetic V1.0]] || [[Media:FPGAPoetic_v1_0_schematics.pdf|FPGA-Poetic v1.0 Schematic PDF]] || [[Media:FPGARack_v1_0.ucf|FPGA-Rack v1.0 UCF Files]] || There are different FPGA mounted: Spartan 6 XC6SLX45, Spartan 6 XC6SLX100, Spartan 6 XC6SLX150<br />
|-<br />
|}<br />
<br />
The boards are compatible with the [[Hardware/FPGARackBackplane|FPGA Rack Backplane]] for interconnecting different boards with the help of the [[Standards/HEI_'VME'_Backplane_Bus|HES-SO Backplane Bus]] and the [[Components/IP/VME|HES-SO VME IP Core]].<br />
<br />
A VHDL test code with the default UCF Files can be found at the EDA SVN Repository:<br />
* https://repos.hevs.ch/svn/eda/VHDL/fgpa_rack<br />
<br />
= Features =<br />
* 1 Ethernet Port<br />
* USB FTDI<br />
* Spartan 6 LX45 - LX100 - LX150<br />
* 2x4 Leds<br />
* 4 User Switches<br />
* 3 Buttons<br />
* 106.25MHz Main Clock<br />
* VME connector 3x32Pin compatible with POETIC Rack backplane<br />
* 2 Mezzanine Connector ARM-EBS and FPGA-EBS compatible<br />
* Powered by USB or VME Power<br />
<br />
= Programmation =<br />
V1.0 is only programmable via JTAG.<br />
<br />
= Links =<br />
* [http://www.xilinx.com/support/documentation/spartan-6.htm Xilinx Spartan 6 Documents]<br />
* [[Standards/VME|VME Description]]<br />
<br />
<br />
[[Category:Hardware]] [[Category:FPGARack]]</div>
Tristan.renon
https://wiki.hevs.ch/uit/index.php5/Hardware/Mezzanine/Poetic
Hardware/Mezzanine/Poetic
2021-10-01T11:57:02Z
<p>Tristan.renon: /* 10 ADCs, 8 DACs */</p>
<hr />
<div>{{TOC right}}<br />
<br />
== 10 ADCs, 8 DACs ==<br />
<br />
This mezzanine was developped for the FPGA Poetic Board during [https://gitlab.hevs.ch/theses/bachelor/jean-nanchen/fpga-developing-board-demonstrator Jean Nanchen's TB] (2021) and used in the NGRW project.<br />
The mezzanine board has 8 SMA connectors (DAC output), 2 connectors 2x10 pins (ADC input), 1 connector 2x5 pins (SPI LVDS) and 1 connector 2x9 pins (SPARE I/O).<br />
<br />
This board is used for the EMVS students project day.<br />
<br />
{|class=wikitable<br />
|- <br />
! Version || Photo || Schematic<br />
|-<br />
| V1.0 || [[File:Poetic Mezza ADC DAC.png|200px|ADC-DAC Mezzanine]] || [[Media:FPGA_Mezza_ADC_DAC_schematic.pdf|FPGA ADC DAC Mezza Schematic PDF]]<br />
|}<br />
<br />
=== ADCs ===<br />
The [https://www.ti.com/product/ADS7886 ADS7886] is a 6 12-Bit, 1-MSPS ADC.<br />
<br />
<br />
=== DACs ===<br />
The [https://www.ti.com/product/DAC084S085 DAC084S085] is a Quad 8-Bit DAC with a serial interface that is compatible with standard SPI,<br />
QSPI, MICROWIRE, and DSP interfaces.<br />
<br />
[[Category:Hardware]] [[Category:Mezzanine]]</div>
Tristan.renon
https://wiki.hevs.ch/uit/index.php5/File:FPGA_Mezza_ADC_DAC_schematic.pdf
File:FPGA Mezza ADC DAC schematic.pdf
2021-10-01T11:44:49Z
<p>Tristan.renon: </p>
<hr />
<div></div>
Tristan.renon
https://wiki.hevs.ch/uit/index.php5/Hardware/FPGAPoetic
Hardware/FPGAPoetic
2021-10-01T11:38:31Z
<p>Tristan.renon: </p>
<hr />
<div>{{TOC right}}<br />
<br />
The basic idea behind this board is to have a FPGA board that interface a VME connector compatible with the POETIC Rack backplane.<br />
<br />
{|class=wikitable<br />
|-<br />
! Type || FPGA Poetic || Schematic || UCF || Description<br />
|-<br />
| V1.0 || [[File:FpgaPoetic.png|200px|FPGA Poetic V1.0]] || [[Media:FPGAPoetic_v1_0_schematics.pdf|FPGA-Poetic v1.0 Schematic PDF]] || [[Media:FPGARack_v1_0.ucf|FPGA-Rack v1.0 UCF Files]] || There are different FPGA mounted: Spartan 6 XC6SLX45, Spartan 6 XC6SLX100, Spartan 6 XC6SLX150<br />
|-<br />
|}<br />
<br />
The boards are compatible with the [[Hardware/FPGARackBackplane|FPGA Rack Backplane]] for interconnecting different boards with the help of the [[Standards/HEI_'VME'_Backplane_Bus|HES-SO Backplane Bus]] and the [[Components/IP/VME|HES-SO VME IP Core]].<br />
<br />
A VHDL test code with the default UCF Files can be found at the EDA SVN Repository:<br />
* https://repos.hevs.ch/svn/eda/VHDL/fgpa_rack<br />
<br />
= Features =<br />
* 1 Ethernet Port<br />
* USB FTDI<br />
* Spartan 6 LX45 - LX100 - LX150<br />
* 2x4 Leds<br />
* 4 User Switches<br />
* 3 Buttons<br />
* 106.25MHz Main Clock<br />
* VME connector 3x32Pin compatible with POETIC Rack backplane<br />
* 2 Mezzanine Connector ARM-EBS and FPGA-EBS compatible<br />
* Powered by USB or VME Power<br />
<br />
= Programmation =<br />
V1.0 is only programmable via JTAG.<br />
<br />
= Links =<br />
* [http://www.xilinx.com/support/documentation/spartan-6.htm Xilinx Spartan 6 Documents]<br />
* [[Standards/VME|VME Description]]<br />
<br />
<br />
[[Category:Hardware]] [[Category:FPGARack]]</div>
Tristan.renon
https://wiki.hevs.ch/uit/index.php5/Hardware/FPGAPoetic
Hardware/FPGAPoetic
2021-10-01T11:35:45Z
<p>Tristan.renon: </p>
<hr />
<div>{{TOC right}}<br />
<br />
The basic idea behind this board is to have a FPGA board that interface a VME connector compatible with the POETIC Rack backplane.<br />
<br />
{|class=wikitable<br />
|-<br />
! Type || FPGA Poetic || Schematic || UCF || Description<br />
|-<br />
| V1.0 || [[File:FPGA_Poetic_v1_0.png|200px|FPGA Poetic V1.0]] || [[Media:FPGAPoetic_v1_0_schematics.pdf|FPGA-Poetic v1.0 Schematic PDF]] || [[Media:FPGARack_v1_0.ucf|FPGA-Rack v1.0 UCF Files]] || There are different FPGA mounted: Spartan 6 XC6SLX45, Spartan 6 XC6SLX100, Spartan 6 XC6SLX150<br />
|-<br />
|}<br />
<br />
The boards are compatible with the [[Hardware/FPGARackBackplane|FPGA Rack Backplane]] for interconnecting different boards with the help of the [[Standards/HEI_'VME'_Backplane_Bus|HES-SO Backplane Bus]] and the [[Components/IP/VME|HES-SO VME IP Core]].<br />
<br />
A VHDL test code with the default UCF Files can be found at the EDA SVN Repository:<br />
* https://repos.hevs.ch/svn/eda/VHDL/fgpa_rack<br />
<br />
= Features =<br />
* 1 Ethernet Port<br />
* USB FTDI<br />
* Spartan 6 LX45 - LX100 - LX150<br />
* 2x4 Leds<br />
* 4 User Switches<br />
* 3 Buttons<br />
* 106.25MHz Main Clock<br />
* VME connector 3x32Pin compatible with POETIC Rack backplane<br />
* 2 Mezzanine Connector ARM-EBS and FPGA-EBS compatible<br />
* Powered by USB or VME Power<br />
<br />
= Programmation =<br />
V1.0 is only programmable via JTAG.<br />
<br />
= Links =<br />
* [http://www.xilinx.com/support/documentation/spartan-6.htm Xilinx Spartan 6 Documents]<br />
* [[Standards/VME|VME Description]]<br />
<br />
<br />
[[Category:Hardware]] [[Category:FPGARack]]</div>
Tristan.renon
https://wiki.hevs.ch/uit/index.php5/Hardware/FPGAPoetic
Hardware/FPGAPoetic
2021-10-01T11:27:23Z
<p>Tristan.renon: </p>
<hr />
<div>{{TOC right}}<br />
<br />
The basic idea behind this board is to have a development FPGA board, with a choice of big FPGA's and a VME compatible 2U Rack connector. The [[Hardware/Stock_FPGA-Rack|stock]] can be verified and updated on-line.<br />
<br />
{|class=wikitable<br />
|-<br />
! Type || FPGA Poetic || Schematic || UCF || Description<br />
|-<br />
| V1.0 || [[File:FPGA_Poetic_v1_0.png|200px|FPGA Poetic V1.0]] || [[Media:FPGAPoetic_v1_0_schematics.pdf|FPGA-Poetic v1.0 Schematic PDF]] || [[Media:FPGARack_v1_0.ucf|FPGA-Rack v1.0 UCF Files]] || There are different FPGA mounted: Spartan 6 XC6SLX45, Spartan 6 XC6SLX100, Spartan 6 XC6SLX150<br />
|-<br />
|}<br />
<br />
The boards are compatible with the [[Hardware/FPGARackBackplane|FPGA Rack Backplane]] for interconnecting different boards with the help of the [[Standards/HEI_'VME'_Backplane_Bus|HES-SO Backplane Bus]] and the [[Components/IP/VME|HES-SO VME IP Core]].<br />
<br />
A VHDL test code with the default UCF Files can be found at the EDA SVN Repository:<br />
* https://repos.hevs.ch/svn/eda/VHDL/fgpa_rack<br />
<br />
= Features =<br />
* 1 Ethernet Port<br />
* USB FTDI<br />
* Spartan 6 LX45 - LX100 - LX150<br />
* 2x4 Leds<br />
* 4 User Switches<br />
* 3 Buttons<br />
* 106.25MHz Main Clock<br />
* VME connector 3x32Pin compatible with POETIC Rack backplane<br />
* 2 Mezzanine Connector ARM-EBS and FPGA-EBS compatible<br />
* Powered by USB or VME Power<br />
<br />
= Programmation =<br />
V1.0 is only programmable via JTAG.<br />
<br />
= Links =<br />
* [http://www.xilinx.com/support/documentation/spartan-6.htm Xilinx Spartan 6 Documents]<br />
* [[Standards/VME|VME Description]]<br />
<br />
<br />
[[Category:Hardware]] [[Category:FPGARack]]</div>
Tristan.renon
https://wiki.hevs.ch/uit/index.php5/Hardware/FPGAPoetic
Hardware/FPGAPoetic
2021-10-01T11:25:52Z
<p>Tristan.renon: </p>
<hr />
<div>{{TOC right}}<br />
<br />
The basic idea behind this board is to have a development FPGA board, with a choice of big FPGA's and a VME compatible 2U Rack connector. The [[Hardware/Stock_FPGA-Rack|stock]] can be verified and updated on-line.<br />
<br />
{|class=wikitable<br />
|-<br />
! Type || FPGA Rack || Schematic || UCF || Description<br />
|-<br />
| V1.0 || [[File:FPGA_Poetic_v1_0.png|200px|FPGA Poetic V1.0]] || [[Media:FPGAPoetic_v1_0_schematics.pdf|FPGA-Poetic v1.0 Schematic PDF]] || [[Media:FPGARack_v1_0.ucf|FPGA-Rack v1.0 UCF Files]] || There are different FPGA mounted: Spartan 6 XC6SLX45, Spartan 6 XC6SLX100, Spartan 6 XC6SLX150<br />
|-<br />
|}<br />
<br />
The boards are compatible with the [[Hardware/FPGARackBackplane|FPGA Rack Backplane]] for interconnecting different boards with the help of the [[Standards/HEI_'VME'_Backplane_Bus|HES-SO Backplane Bus]] and the [[Components/IP/VME|HES-SO VME IP Core]].<br />
<br />
A VHDL test code with the default UCF Files can be found at the EDA SVN Repository:<br />
* https://repos.hevs.ch/svn/eda/VHDL/fgpa_rack<br />
<br />
= Features =<br />
* 1 Ethernet Port<br />
* USB FTDI<br />
* Spartan 6 LX45 - LX100 - LX150<br />
* 2x4 Leds<br />
* 4 User Switches<br />
* 3 Buttons<br />
* 106.25MHz Main Clock<br />
* VME connector 3x32Pin compatible with POETIC Rack backplane<br />
* 2 Mezzanine Connector ARM-EBS and FPGA-EBS compatible<br />
* Powered by USB or VME Power<br />
<br />
= Programmation =<br />
V1.0 is only programmable via JTAG.<br />
<br />
= Links =<br />
* [http://www.xilinx.com/support/documentation/spartan-6.htm Xilinx Spartan 6 Documents]<br />
* [[Standards/VME|VME Description]]<br />
<br />
<br />
[[Category:Hardware]] [[Category:FPGARack]]</div>
Tristan.renon
https://wiki.hevs.ch/uit/index.php5/File:FPGAPoetic_v1_0_schematics.pdf
File:FPGAPoetic v1 0 schematics.pdf
2021-10-01T11:25:29Z
<p>Tristan.renon: </p>
<hr />
<div></div>
Tristan.renon
https://wiki.hevs.ch/uit/index.php5/File:FpgaPoetic.png
File:FpgaPoetic.png
2021-10-01T11:21:59Z
<p>Tristan.renon: </p>
<hr />
<div></div>
Tristan.renon
https://wiki.hevs.ch/uit/index.php5/Hardware/Mezzanine/Poetic
Hardware/Mezzanine/Poetic
2021-10-01T09:02:51Z
<p>Tristan.renon: Created page with "{{TOC right}} == 10 ADCs, 8 DACs == This 8-channel Analog to Digital Converter (ADC) circuit has been used in the [http://www.dev-audio.com/products/microcone/ microcone] pr..."</p>
<hr />
<div>{{TOC right}}<br />
<br />
== 10 ADCs, 8 DACs ==<br />
<br />
This 8-channel Analog to Digital Converter (ADC) circuit has been used in the [http://www.dev-audio.com/products/microcone/ microcone] project.<br />
The mezzanine board has four 3.5mm jack input connectors.<br />
<br />
This board is used for the EMVS students project day.<br />
<br />
{|class=wikitable<br />
|- <br />
! Version || Photo || Schematic || Description<br />
|-<br />
| V1.0 || [[File:Poetic Mezza ADC DAC.png|200px|ADC-DAC Mezzanine]] || [[Media:FPGA_Mezza_ADC_schematic.pdf|FPGA ADC Mezza Schematic PDF]] || 8 Channel (4 * Stereo Jack input) ADC Mezzanine Extension. It uses the [[Media:ADC_Cirrus_CS5368.pdf|Cirrus Logic CS5368 ADC]]<br />
|}<br />
<br />
=== ADCs ===<br />
The [https://www.ti.com/product/ADS7886 ADS7886] is a 6 12-Bit, 1-MSPS ADC.<br />
<br />
<br />
=== DACs ===<br />
<br />
<br />
[[Category:Hardware]] [[Category:Mezzanine]]</div>
Tristan.renon
https://wiki.hevs.ch/uit/index.php5/File:Poetic_Mezza_ADC_DAC.png
File:Poetic Mezza ADC DAC.png
2021-10-01T09:01:50Z
<p>Tristan.renon: </p>
<hr />
<div></div>
Tristan.renon
https://wiki.hevs.ch/uit/index.php5/Hardware
Hardware
2021-10-01T08:56:32Z
<p>Tristan.renon: /* Mezzanine Boards */</p>
<hr />
<div>{{TOC right}}<br />
<br />
''' Here your can find various information about the Hardware used at HES-SO Valais Wallis '''<br />
<br />
== Stock ==<br />
'''If you need some Hardware parts, ask [[User:Francois.corthay|François Corthay]], [[User:Clm|Clausen Michael]] or [[User:Sap|Sartoretti Pascal]]'''<br />
and check the [[Inventory]]<br />
<br />
== PCB Design ==<br />
Check out our [[Hardware/Design/Rules|Design Rules]] and our [[Tools/Altium Designer|Altium Designer Manual]].<br />
<br />
== Ordering ==<br />
If you need to order some material, check the [[Hardware/OrderingGuide|Hardware Ordering Guide]].<br />
<br />
== Documentation ==<br />
Information about EDA Hardware can be found here: <code>I:\Admin\SI-ET\Institut\Infrastructure\Labos\A309\FPGA\</code><br />
<br />
== FPGA Boards ==<br />
=== FPGA EBS ===<br />
* [[Hardware/FPGAEBS|HES-SO FPGA EBS Board]]<br />
=== FPGA Rack ===<br />
* [[Hardware/FPGARack|HES-SO FPGA Rack Board]] - ''XC6SLX45/100/150''<br />
* [[Hardware/FPGARackZynqADDAV1|HES-SO FPGA Rack Zynq AD/DA (ZynqADDA)]] - ''XC7Z020''<br />
* [[Hardware/FPGARackHiRADDAV1|HES-SO FPGA Rack Hi-Res AD/DA (HiRADDA)]] & [[Hardware/FPGARackHiRADDAPOWERV1|Power board (HiRADDA Power)]] - ''XC7K160T / 2x 4MSPS 24bit ADC / 1x 500MSPS 16bit DAC / 256MiB DDR3 SDRAM / FLASH / M/FRAM''<br />
* [[Hardware/FPGARackHiSADDAV1|HES-SO FPGA Rack Hi-Speed AD/DA (HiSADDA)]] - ''XC7K160T / 2x 500MSPS 12bit ADC / 2x 400MSPS 16bit DAC / 1GiB DDR3 SDRAM / FLASH''<br />
* [[Hardware/FPGARack4ethernet|HES-SO FPGA Rack 4ethernet]] - ''XC6SLX45/100/150''<br />
* [[Hardware/FPGARackEdison|HES-SO FPGA Rack Edison]] - ''AGL1000''<br />
* [[Hardware/FPGARackADDAV1|HES-SO FPGA Rack AD/DA (OLGMADDA)]] - <span style="color:#A02020">[''Deprecated'']</span><br />
<br />
=== FPGA Poetic ===<br />
* [[Hardware/FPGAPoetic|Industrial Electronics & Drives Poetic FPGA Board]] - ''XC6SLX45/100/150''<br />
<br />
=== CubeSat ===<br />
<br />
* [[Hardware/CubeSat Gumstix| CubeSat + Gumstix]] - ''processing board''<br />
* [[Hardware/CubeSat RPi| CubeSat + Raspberry Pi zero]] - On-Board Computer (OBC)<br />
<br />
=== CanSat ===<br />
* [http://wiki.hevs.ch/fsi/index.php5/HiRel/CanSat/Master_FPGA CanSat Master FPGA] - ''Spartan 6 XC6SLX9 and 8Mb M25P80 SPI PROM''<br />
<br />
=== DevKits ===<br />
* [[Hardware/Enterpoint_Drigmorn4|Enterpoint Drigmorn4 Spartan6 starter kit]]<br />
* [[Hardware/Actel_CoreMP7|Actel CoreMP7 Dev-Kit]]<br />
* [[Hardware/Actel_SmartFusion|Actel SmartFusion Dev-Kit]]<br />
* [[Hardware/Beckhoff_FB1130|Beckhoff EtherCAT FB1130]]<br />
* [[Hardware/Trenz_TE0720|Trenz Electronic Zynq Module TE0720]]<br />
<br />
=== MiniBioDet ===<br />
* [[Hardware/MiniBioDet| MiniBioDet FPGA Board ]] - ''20/40/65/80 MSPS 16bit ADC / 175 MSPS 14bit DAC / Bluetooth Smart''<br />
<br />
== Processor Boards ==<br />
=== CPU Boards ===<br />
* [[Hardware/STM32F746G-DISCO|HES-SO STM32F7 Board with extension]]<br />
* [[Hardware/ARMEBS|HES-SO ARMEBS Board]]<br />
* [[Hardware/RasPiB|Raspberry Pi ARM11 Single Board Computer]]<br />
* [[Hardware/TQMa28|TQM28a ARM9 module with i.MX28 from Freescale]]<br />
* [[Hardware/Galileo|Intel Galileo Arduino board]]<br />
* [[Hardware/PCEnginesAPU1D4|PC Engines APU1D4]]<br />
* [[Hardware/Gumstix|Gumstix]]<br />
* [[Hardware/RasPi3|Raspberry Pi 3 - cours FET]]<br />
<br />
=== Pic Boards ===<br />
* [[Hardware/PIcEBS|HES-SO PIC EBS Board]]<br />
<br />
== Signal Boards ==<br />
* [[Hardware/8CH4IOHFAnalogMuxBoard|HF Analog Mux/Demux Board (8 Channels, 4 I/O)]]<br />
<br />
== Rack Boards ==<br />
=== Backplanes ===<br />
* [[Hardware/FPGARackBackplane|HEI Rack Backplane]]<br />
<br />
=== Slave ===<br />
* [[Hardware/FPGARackDebug|HEI Rack Debug Board]]<br />
* [[Hardware/RackParallelPortBackplane|HEI Rack HEB Backplane]]<br />
* [[Hardware/FPGARackHiSADDAV1|HEI Rack AD/DA (OLGMADDA)]] - <span style="color:#A02020">[''Deprecated'']</span><br />
* [[Hardware/FPGARackZynqADDAV1|HEI Rack Zynq AD/DA (ZynqADDA)]]<br />
* [[Hardware/FPGARackHiSADDAV1|HEI Rack Hi-Speed AD/DA (HiSADDA)]]<br />
* [[Hardware/FPGARackRelayCtrlV1|HEI Rack Relay Ctrl]]<br />
* [[Hardware/HEIRackRF|HEI Rack RF]]<br />
<br />
== Mezzanine Boards ==<br />
* [[Hardware/Mezzanine/Ethertap|EBS Mezza Parallel I/O and Ethernet tap]]<br />
* [[Hardware/Mezzanine/ADC|EBS Mezza 8-channel ADC]]<br />
* [[Hardware/Mezzanine/high-speed AD-DA|EBS Mezza high-speed AD-DA]] - <span style="color:#A02020">[''Deprecated'']</span><br />
* [[Hardware/Mezzanine/audio AD-DA|EBS Mezza audio AD-DA]]<br />
* [[Hardware/Mezzanine/PWM|EBS Mezza PWM]]<br />
* [[Hardware/Mezzanine/Poetic|EBS Mezza 20 ADCs, 8 DACs]]<br />
<br />
== Extension Boards == <br />
* [[Hardware/Extention/Passive_Ethertap|HES-SO Passive Ethernet Measurement Point]]<br />
<br />
== Parallelport Boards ==<br />
Boards with a Paralellport connector compatible with the [[Hardware/FPGAEBS|FPGA EBS]] board.<br />
<br />
* [[Hardware/Parallelport/motor|EBS Motor (Clock)]]<br />
* [[Hardware/Parallelport/PTP|PTP]]<br />
* [[Hardware/Parallelport/DAC2|2-channel DAC]]<br />
* [[Hardware/Parallelport/heb_gia|GIA (Generic Inverting Amplifier)]]<br />
* [[Hardware/Parallelport/Audio_ADC_DAC|Audio ADC DAC]]<br />
<br />
=== HEB ===<br />
<br />
'''H'''EI '''E'''ducational '''B'''oards feature a well defined form factor with a Paralellport connector compatible with the [[Hardware/FPGAEBS|FPGA EBS]] board and defined holes for mounting.<br />
<br />
* [[Hardware/Parallelport/heb_lcd|LCD (with 4 buttons and 8 LEDs)]]<br />
* [[Hardware/Parallelport/heb_rotary|4 rotary switches]]<br />
* [[Hardware/Parallelport/heb_synchro|Synchro]]<br />
* [[Hardware/Parallelport/heb_microphone|Beeper and microphone]]<br />
* [[Hardware/Parallelport/heb_jtag|JTAG and RS232]]<br />
* [[Hardware/Parallelport/heb_rs232|RS232]]<br />
* [[Hardware/Parallelport/heb_matrix|7 x 10 LED matrix]]<br />
<br />
== Sensor Boards ==<br />
=== SmartHome ===<br />
* [[Hardware/Develco/index|Develco Products]]<br />
=== GPS ===<br />
* [[Hardware/Sensor/GPS_Navman|Navman Jupiter30]]<br />
=== Acceleration ===<br />
* [[Hardware/Sensor/JoyWarrior J24F14|JoyWarrior JW24F14]]<br />
=== Environment ===<br />
* [http://wiki.hevs.ch/fsi/index.php5/HiRel/CanSat/Slave_Sensors CanSat Slave Sensor (Humidity, Temperature, Pression) ]<br />
<br />
== Programmers / Interfaces ==<br />
* [[Hardware/Programmers|FPGA Programmers]]<br />
* [[Hardware/Interfaces|USB to CAN Interface]]<br />
<br />
== Buses ==<br />
* [[Hardware/Bus/i2c| i2c]]<br />
[[Category:Hardware]]</div>
Tristan.renon
https://wiki.hevs.ch/uit/index.php5/Hardware/FPGAPoetic
Hardware/FPGAPoetic
2021-10-01T08:52:52Z
<p>Tristan.renon: /* Leds and Buttons */</p>
<hr />
<div>{{TOC right}}<br />
<br />
The basic idea behind this board is to have a development FPGA board, with a choice of big FPGA's and a VME compatible 2U Rack connector. The [[Hardware/Stock_FPGA-Rack|stock]] can be verified and updated on-line.<br />
<br />
{|class=wikitable<br />
|-<br />
! Type || FPGA Rack || Schematic || UCF || Description<br />
|-<br />
| V1.0 || [[File:FPGA_Rack_v1_0.jpg|200px|FPGA Rack V1.0]] || [[Media:FPGARack_v1_0_schematics.pdf|FPGA-Rack v1.0 Schematic PDF]] || [[Media:FPGARack_v1_0.ucf|FPGA-Rack v1.0 UCF Files]] || There are different FPGA mounted: Spartan 6 XC6SLX45, Spartan 6 XC6SLX100, Spartan 6 XC6SLX150<br />
|-<br />
|}<br />
<br />
The boards are compatible with the [[Hardware/FPGARackBackplane|FPGA Rack Backplane]] for interconnecting different boards with the help of the [[Standards/HEI_'VME'_Backplane_Bus|HES-SO Backplane Bus]] and the [[Components/IP/VME|HES-SO VME IP Core]].<br />
<br />
A VHDL test code with the default UCF Files can be found at the EDA SVN Repository:<br />
* https://repos.hevs.ch/svn/eda/VHDL/fgpa_rack<br />
<br />
= Features =<br />
* 1 Ethernet Port<br />
* USB FTDI<br />
* Spartan 6 LX45 - LX100 - LX150<br />
* 2x4 Leds<br />
* 4 User Switches<br />
* 3 Buttons<br />
* 106.25MHz Main Clock<br />
* VME connector 3x32Pin compatible with POETIC Rack backplane<br />
* 2 Mezzanine Connector ARM-EBS and FPGA-EBS compatible<br />
* Powered by USB or VME Power<br />
<br />
= Programmation =<br />
V1.0 is only programmable via JTAG.<br />
<br />
= Links =<br />
* [http://www.xilinx.com/support/documentation/spartan-6.htm Xilinx Spartan 6 Documents]<br />
* [[Standards/VME|VME Description]]<br />
<br />
<br />
[[Category:Hardware]] [[Category:FPGARack]]</div>
Tristan.renon
https://wiki.hevs.ch/uit/index.php5/Hardware/FPGAPoetic
Hardware/FPGAPoetic
2021-10-01T08:52:35Z
<p>Tristan.renon: /* Features */</p>
<hr />
<div>{{TOC right}}<br />
<br />
The basic idea behind this board is to have a development FPGA board, with a choice of big FPGA's and a VME compatible 2U Rack connector. The [[Hardware/Stock_FPGA-Rack|stock]] can be verified and updated on-line.<br />
<br />
{|class=wikitable<br />
|-<br />
! Type || FPGA Rack || Schematic || UCF || Description<br />
|-<br />
| V1.0 || [[File:FPGA_Rack_v1_0.jpg|200px|FPGA Rack V1.0]] || [[Media:FPGARack_v1_0_schematics.pdf|FPGA-Rack v1.0 Schematic PDF]] || [[Media:FPGARack_v1_0.ucf|FPGA-Rack v1.0 UCF Files]] || There are different FPGA mounted: Spartan 6 XC6SLX45, Spartan 6 XC6SLX100, Spartan 6 XC6SLX150<br />
|-<br />
|}<br />
<br />
The boards are compatible with the [[Hardware/FPGARackBackplane|FPGA Rack Backplane]] for interconnecting different boards with the help of the [[Standards/HEI_'VME'_Backplane_Bus|HES-SO Backplane Bus]] and the [[Components/IP/VME|HES-SO VME IP Core]].<br />
<br />
A VHDL test code with the default UCF Files can be found at the EDA SVN Repository:<br />
* https://repos.hevs.ch/svn/eda/VHDL/fgpa_rack<br />
<br />
= Leds and Buttons =<br />
There are 4 Dil switches and 4 Leds mounted on the FPGARack board. They are not properly indicated 0 - 3 therefore see the image below.<br />
<br />
[[File:FPGA_Rack_v1_0_LedsButtons.jpg|200px|FPGA Rack V1.0 Leds and Buttons]]<br />
<br />
= Features =<br />
* 1 Ethernet Port<br />
* USB FTDI<br />
* Spartan 6 LX45 - LX100 - LX150<br />
* 2x4 Leds<br />
* 4 User Switches<br />
* 3 Buttons<br />
* 106.25MHz Main Clock<br />
* VME connector 3x32Pin compatible with POETIC Rack backplane<br />
* 2 Mezzanine Connector ARM-EBS and FPGA-EBS compatible<br />
* Powered by USB or VME Power<br />
<br />
= Programmation =<br />
V1.0 is only programmable via JTAG.<br />
<br />
= Links =<br />
* [http://www.xilinx.com/support/documentation/spartan-6.htm Xilinx Spartan 6 Documents]<br />
* [[Standards/VME|VME Description]]<br />
<br />
<br />
[[Category:Hardware]] [[Category:FPGARack]]</div>
Tristan.renon
https://wiki.hevs.ch/uit/index.php5/Hardware/FPGAPoetic
Hardware/FPGAPoetic
2021-10-01T08:49:16Z
<p>Tristan.renon: /* Programmation */</p>
<hr />
<div>{{TOC right}}<br />
<br />
The basic idea behind this board is to have a development FPGA board, with a choice of big FPGA's and a VME compatible 2U Rack connector. The [[Hardware/Stock_FPGA-Rack|stock]] can be verified and updated on-line.<br />
<br />
{|class=wikitable<br />
|-<br />
! Type || FPGA Rack || Schematic || UCF || Description<br />
|-<br />
| V1.0 || [[File:FPGA_Rack_v1_0.jpg|200px|FPGA Rack V1.0]] || [[Media:FPGARack_v1_0_schematics.pdf|FPGA-Rack v1.0 Schematic PDF]] || [[Media:FPGARack_v1_0.ucf|FPGA-Rack v1.0 UCF Files]] || There are different FPGA mounted: Spartan 6 XC6SLX45, Spartan 6 XC6SLX100, Spartan 6 XC6SLX150<br />
|-<br />
|}<br />
<br />
The boards are compatible with the [[Hardware/FPGARackBackplane|FPGA Rack Backplane]] for interconnecting different boards with the help of the [[Standards/HEI_'VME'_Backplane_Bus|HES-SO Backplane Bus]] and the [[Components/IP/VME|HES-SO VME IP Core]].<br />
<br />
A VHDL test code with the default UCF Files can be found at the EDA SVN Repository:<br />
* https://repos.hevs.ch/svn/eda/VHDL/fgpa_rack<br />
<br />
= Leds and Buttons =<br />
There are 4 Dil switches and 4 Leds mounted on the FPGARack board. They are not properly indicated 0 - 3 therefore see the image below.<br />
<br />
[[File:FPGA_Rack_v1_0_LedsButtons.jpg|200px|FPGA Rack V1.0 Leds and Buttons]]<br />
<br />
= Features =<br />
* 2 Port Ethernet (one PTP physical)<br />
* USB FTDI<br />
* 2 UART<br />
* Flash 128Mb - 512Mb<br />
* Ram 128Mb - 256Mb<br />
* Spartan 6 LX45 - LX100 - LX150<br />
* 4 Leds<br />
* 4 Dil Switches<br />
* 1 Button<br />
* 106.25MHz Main Clock<br />
* VME compatible connector 3x32Pin<br />
* 2 Debug connectors 2x50Pin<br />
* 2 Mezzanine Connector ARM-EBS and FPGA-EBS compatible<br />
* Powered by USB or VME Power<br />
<br />
= Programmation =<br />
V1.0 is only programmable via JTAG.<br />
<br />
= Links =<br />
* [http://www.xilinx.com/support/documentation/spartan-6.htm Xilinx Spartan 6 Documents]<br />
* [[Standards/VME|VME Description]]<br />
<br />
<br />
[[Category:Hardware]] [[Category:FPGARack]]</div>
Tristan.renon
https://wiki.hevs.ch/uit/index.php5/Hardware/FPGAPoetic
Hardware/FPGAPoetic
2021-10-01T08:48:44Z
<p>Tristan.renon: /* VME connector logic levels */</p>
<hr />
<div>{{TOC right}}<br />
<br />
The basic idea behind this board is to have a development FPGA board, with a choice of big FPGA's and a VME compatible 2U Rack connector. The [[Hardware/Stock_FPGA-Rack|stock]] can be verified and updated on-line.<br />
<br />
{|class=wikitable<br />
|-<br />
! Type || FPGA Rack || Schematic || UCF || Description<br />
|-<br />
| V1.0 || [[File:FPGA_Rack_v1_0.jpg|200px|FPGA Rack V1.0]] || [[Media:FPGARack_v1_0_schematics.pdf|FPGA-Rack v1.0 Schematic PDF]] || [[Media:FPGARack_v1_0.ucf|FPGA-Rack v1.0 UCF Files]] || There are different FPGA mounted: Spartan 6 XC6SLX45, Spartan 6 XC6SLX100, Spartan 6 XC6SLX150<br />
|-<br />
|}<br />
<br />
The boards are compatible with the [[Hardware/FPGARackBackplane|FPGA Rack Backplane]] for interconnecting different boards with the help of the [[Standards/HEI_'VME'_Backplane_Bus|HES-SO Backplane Bus]] and the [[Components/IP/VME|HES-SO VME IP Core]].<br />
<br />
A VHDL test code with the default UCF Files can be found at the EDA SVN Repository:<br />
* https://repos.hevs.ch/svn/eda/VHDL/fgpa_rack<br />
<br />
= Leds and Buttons =<br />
There are 4 Dil switches and 4 Leds mounted on the FPGARack board. They are not properly indicated 0 - 3 therefore see the image below.<br />
<br />
[[File:FPGA_Rack_v1_0_LedsButtons.jpg|200px|FPGA Rack V1.0 Leds and Buttons]]<br />
<br />
= Features =<br />
* 2 Port Ethernet (one PTP physical)<br />
* USB FTDI<br />
* 2 UART<br />
* Flash 128Mb - 512Mb<br />
* Ram 128Mb - 256Mb<br />
* Spartan 6 LX45 - LX100 - LX150<br />
* 4 Leds<br />
* 4 Dil Switches<br />
* 1 Button<br />
* 106.25MHz Main Clock<br />
* VME compatible connector 3x32Pin<br />
* 2 Debug connectors 2x50Pin<br />
* 2 Mezzanine Connector ARM-EBS and FPGA-EBS compatible<br />
* Powered by USB or VME Power<br />
<br />
= Programmation =<br />
This board can be programmed in 2 ways,<br />
* first the FPGA can be directly programmed<br />
* second the FPGA can be programmed via the onboard Flash memory<br />
<br />
For more explanation see at the Howto below:<br />
* [[Hardware/FPGARack/Programmation|FPGA Rack Programmation]]<br />
<br />
= Links =<br />
* [http://www.xilinx.com/support/documentation/spartan-6.htm Xilinx Spartan 6 Documents]<br />
* [[Standards/VME|VME Description]]<br />
<br />
<br />
[[Category:Hardware]] [[Category:FPGARack]]</div>
Tristan.renon
https://wiki.hevs.ch/uit/index.php5/Hardware/FPGAPoetic
Hardware/FPGAPoetic
2021-10-01T08:48:13Z
<p>Tristan.renon: /* Limitation */</p>
<hr />
<div>{{TOC right}}<br />
<br />
The basic idea behind this board is to have a development FPGA board, with a choice of big FPGA's and a VME compatible 2U Rack connector. The [[Hardware/Stock_FPGA-Rack|stock]] can be verified and updated on-line.<br />
<br />
{|class=wikitable<br />
|-<br />
! Type || FPGA Rack || Schematic || UCF || Description<br />
|-<br />
| V1.0 || [[File:FPGA_Rack_v1_0.jpg|200px|FPGA Rack V1.0]] || [[Media:FPGARack_v1_0_schematics.pdf|FPGA-Rack v1.0 Schematic PDF]] || [[Media:FPGARack_v1_0.ucf|FPGA-Rack v1.0 UCF Files]] || There are different FPGA mounted: Spartan 6 XC6SLX45, Spartan 6 XC6SLX100, Spartan 6 XC6SLX150<br />
|-<br />
|}<br />
<br />
The boards are compatible with the [[Hardware/FPGARackBackplane|FPGA Rack Backplane]] for interconnecting different boards with the help of the [[Standards/HEI_'VME'_Backplane_Bus|HES-SO Backplane Bus]] and the [[Components/IP/VME|HES-SO VME IP Core]].<br />
<br />
A VHDL test code with the default UCF Files can be found at the EDA SVN Repository:<br />
* https://repos.hevs.ch/svn/eda/VHDL/fgpa_rack<br />
<br />
= Leds and Buttons =<br />
There are 4 Dil switches and 4 Leds mounted on the FPGARack board. They are not properly indicated 0 - 3 therefore see the image below.<br />
<br />
[[File:FPGA_Rack_v1_0_LedsButtons.jpg|200px|FPGA Rack V1.0 Leds and Buttons]]<br />
<br />
= Features =<br />
* 2 Port Ethernet (one PTP physical)<br />
* USB FTDI<br />
* 2 UART<br />
* Flash 128Mb - 512Mb<br />
* Ram 128Mb - 256Mb<br />
* Spartan 6 LX45 - LX100 - LX150<br />
* 4 Leds<br />
* 4 Dil Switches<br />
* 1 Button<br />
* 106.25MHz Main Clock<br />
* VME compatible connector 3x32Pin<br />
* 2 Debug connectors 2x50Pin<br />
* 2 Mezzanine Connector ARM-EBS and FPGA-EBS compatible<br />
* Powered by USB or VME Power<br />
<br />
= VME connector logic levels =<br />
The I/O bank which interfaces the VME connector<br />
(and the little black connectors)<br />
can be powered with 3.3V or with 2.5V.<br />
A zero-Ohm resistor has to be soldered at the proper place near the FPGA.<br />
<br />
= Programmation =<br />
This board can be programmed in 2 ways,<br />
* first the FPGA can be directly programmed<br />
* second the FPGA can be programmed via the onboard Flash memory<br />
<br />
For more explanation see at the Howto below:<br />
* [[Hardware/FPGARack/Programmation|FPGA Rack Programmation]]<br />
<br />
= Links =<br />
* [http://www.xilinx.com/support/documentation/spartan-6.htm Xilinx Spartan 6 Documents]<br />
* [[Standards/VME|VME Description]]<br />
<br />
<br />
[[Category:Hardware]] [[Category:FPGARack]]</div>
Tristan.renon
https://wiki.hevs.ch/uit/index.php5/Hardware/FPGAPoetic
Hardware/FPGAPoetic
2021-10-01T08:47:52Z
<p>Tristan.renon: Created page with "{{TOC right}} The basic idea behind this board is to have a development FPGA board, with a choice of big FPGA's and a VME compatible 2U Rack connector. The [[Hardware/Stock_F..."</p>
<hr />
<div>{{TOC right}}<br />
<br />
The basic idea behind this board is to have a development FPGA board, with a choice of big FPGA's and a VME compatible 2U Rack connector. The [[Hardware/Stock_FPGA-Rack|stock]] can be verified and updated on-line.<br />
<br />
{|class=wikitable<br />
|-<br />
! Type || FPGA Rack || Schematic || UCF || Description<br />
|-<br />
| V1.0 || [[File:FPGA_Rack_v1_0.jpg|200px|FPGA Rack V1.0]] || [[Media:FPGARack_v1_0_schematics.pdf|FPGA-Rack v1.0 Schematic PDF]] || [[Media:FPGARack_v1_0.ucf|FPGA-Rack v1.0 UCF Files]] || There are different FPGA mounted: Spartan 6 XC6SLX45, Spartan 6 XC6SLX100, Spartan 6 XC6SLX150<br />
|-<br />
|}<br />
<br />
The boards are compatible with the [[Hardware/FPGARackBackplane|FPGA Rack Backplane]] for interconnecting different boards with the help of the [[Standards/HEI_'VME'_Backplane_Bus|HES-SO Backplane Bus]] and the [[Components/IP/VME|HES-SO VME IP Core]].<br />
<br />
A VHDL test code with the default UCF Files can be found at the EDA SVN Repository:<br />
* https://repos.hevs.ch/svn/eda/VHDL/fgpa_rack<br />
<br />
= Limitation =<br />
There are Boards with 3 types of FPGA's on it; ''XC6SLX45'', ''XC6SLX100'' and ''XC6SLX150''.<br />
{{WarningBox|content=Mezzanine Pin <code>T8</code> - <code>MEZ_PB19</code> can't be used if a ''XC6SLX100'' is mounted.}}<br />
<br />
= Leds and Buttons =<br />
There are 4 Dil switches and 4 Leds mounted on the FPGARack board. They are not properly indicated 0 - 3 therefore see the image below.<br />
<br />
[[File:FPGA_Rack_v1_0_LedsButtons.jpg|200px|FPGA Rack V1.0 Leds and Buttons]]<br />
<br />
= Features =<br />
* 2 Port Ethernet (one PTP physical)<br />
* USB FTDI<br />
* 2 UART<br />
* Flash 128Mb - 512Mb<br />
* Ram 128Mb - 256Mb<br />
* Spartan 6 LX45 - LX100 - LX150<br />
* 4 Leds<br />
* 4 Dil Switches<br />
* 1 Button<br />
* 106.25MHz Main Clock<br />
* VME compatible connector 3x32Pin<br />
* 2 Debug connectors 2x50Pin<br />
* 2 Mezzanine Connector ARM-EBS and FPGA-EBS compatible<br />
* Powered by USB or VME Power<br />
<br />
= VME connector logic levels =<br />
The I/O bank which interfaces the VME connector<br />
(and the little black connectors)<br />
can be powered with 3.3V or with 2.5V.<br />
A zero-Ohm resistor has to be soldered at the proper place near the FPGA.<br />
<br />
= Programmation =<br />
This board can be programmed in 2 ways,<br />
* first the FPGA can be directly programmed<br />
* second the FPGA can be programmed via the onboard Flash memory<br />
<br />
For more explanation see at the Howto below:<br />
* [[Hardware/FPGARack/Programmation|FPGA Rack Programmation]]<br />
<br />
= Links =<br />
* [http://www.xilinx.com/support/documentation/spartan-6.htm Xilinx Spartan 6 Documents]<br />
* [[Standards/VME|VME Description]]<br />
<br />
<br />
[[Category:Hardware]] [[Category:FPGARack]]</div>
Tristan.renon
https://wiki.hevs.ch/uit/index.php5/Hardware
Hardware
2021-10-01T08:46:52Z
<p>Tristan.renon: /* FPGA Rack */</p>
<hr />
<div>{{TOC right}}<br />
<br />
''' Here your can find various information about the Hardware used at HES-SO Valais Wallis '''<br />
<br />
== Stock ==<br />
'''If you need some Hardware parts, ask [[User:Francois.corthay|François Corthay]], [[User:Clm|Clausen Michael]] or [[User:Sap|Sartoretti Pascal]]'''<br />
and check the [[Inventory]]<br />
<br />
== PCB Design ==<br />
Check out our [[Hardware/Design/Rules|Design Rules]] and our [[Tools/Altium Designer|Altium Designer Manual]].<br />
<br />
== Ordering ==<br />
If you need to order some material, check the [[Hardware/OrderingGuide|Hardware Ordering Guide]].<br />
<br />
== Documentation ==<br />
Information about EDA Hardware can be found here: <code>I:\Admin\SI-ET\Institut\Infrastructure\Labos\A309\FPGA\</code><br />
<br />
== FPGA Boards ==<br />
=== FPGA EBS ===<br />
* [[Hardware/FPGAEBS|HES-SO FPGA EBS Board]]<br />
=== FPGA Rack ===<br />
* [[Hardware/FPGARack|HES-SO FPGA Rack Board]] - ''XC6SLX45/100/150''<br />
* [[Hardware/FPGARackZynqADDAV1|HES-SO FPGA Rack Zynq AD/DA (ZynqADDA)]] - ''XC7Z020''<br />
* [[Hardware/FPGARackHiRADDAV1|HES-SO FPGA Rack Hi-Res AD/DA (HiRADDA)]] & [[Hardware/FPGARackHiRADDAPOWERV1|Power board (HiRADDA Power)]] - ''XC7K160T / 2x 4MSPS 24bit ADC / 1x 500MSPS 16bit DAC / 256MiB DDR3 SDRAM / FLASH / M/FRAM''<br />
* [[Hardware/FPGARackHiSADDAV1|HES-SO FPGA Rack Hi-Speed AD/DA (HiSADDA)]] - ''XC7K160T / 2x 500MSPS 12bit ADC / 2x 400MSPS 16bit DAC / 1GiB DDR3 SDRAM / FLASH''<br />
* [[Hardware/FPGARack4ethernet|HES-SO FPGA Rack 4ethernet]] - ''XC6SLX45/100/150''<br />
* [[Hardware/FPGARackEdison|HES-SO FPGA Rack Edison]] - ''AGL1000''<br />
* [[Hardware/FPGARackADDAV1|HES-SO FPGA Rack AD/DA (OLGMADDA)]] - <span style="color:#A02020">[''Deprecated'']</span><br />
<br />
=== FPGA Poetic ===<br />
* [[Hardware/FPGAPoetic|Industrial Electronics & Drives Poetic FPGA Board]] - ''XC6SLX45/100/150''<br />
<br />
=== CubeSat ===<br />
<br />
* [[Hardware/CubeSat Gumstix| CubeSat + Gumstix]] - ''processing board''<br />
* [[Hardware/CubeSat RPi| CubeSat + Raspberry Pi zero]] - On-Board Computer (OBC)<br />
<br />
=== CanSat ===<br />
* [http://wiki.hevs.ch/fsi/index.php5/HiRel/CanSat/Master_FPGA CanSat Master FPGA] - ''Spartan 6 XC6SLX9 and 8Mb M25P80 SPI PROM''<br />
<br />
=== DevKits ===<br />
* [[Hardware/Enterpoint_Drigmorn4|Enterpoint Drigmorn4 Spartan6 starter kit]]<br />
* [[Hardware/Actel_CoreMP7|Actel CoreMP7 Dev-Kit]]<br />
* [[Hardware/Actel_SmartFusion|Actel SmartFusion Dev-Kit]]<br />
* [[Hardware/Beckhoff_FB1130|Beckhoff EtherCAT FB1130]]<br />
* [[Hardware/Trenz_TE0720|Trenz Electronic Zynq Module TE0720]]<br />
<br />
=== MiniBioDet ===<br />
* [[Hardware/MiniBioDet| MiniBioDet FPGA Board ]] - ''20/40/65/80 MSPS 16bit ADC / 175 MSPS 14bit DAC / Bluetooth Smart''<br />
<br />
== Processor Boards ==<br />
=== CPU Boards ===<br />
* [[Hardware/STM32F746G-DISCO|HES-SO STM32F7 Board with extension]]<br />
* [[Hardware/ARMEBS|HES-SO ARMEBS Board]]<br />
* [[Hardware/RasPiB|Raspberry Pi ARM11 Single Board Computer]]<br />
* [[Hardware/TQMa28|TQM28a ARM9 module with i.MX28 from Freescale]]<br />
* [[Hardware/Galileo|Intel Galileo Arduino board]]<br />
* [[Hardware/PCEnginesAPU1D4|PC Engines APU1D4]]<br />
* [[Hardware/Gumstix|Gumstix]]<br />
* [[Hardware/RasPi3|Raspberry Pi 3 - cours FET]]<br />
<br />
=== Pic Boards ===<br />
* [[Hardware/PIcEBS|HES-SO PIC EBS Board]]<br />
<br />
== Signal Boards ==<br />
* [[Hardware/8CH4IOHFAnalogMuxBoard|HF Analog Mux/Demux Board (8 Channels, 4 I/O)]]<br />
<br />
== Rack Boards ==<br />
=== Backplanes ===<br />
* [[Hardware/FPGARackBackplane|HEI Rack Backplane]]<br />
<br />
=== Slave ===<br />
* [[Hardware/FPGARackDebug|HEI Rack Debug Board]]<br />
* [[Hardware/RackParallelPortBackplane|HEI Rack HEB Backplane]]<br />
* [[Hardware/FPGARackHiSADDAV1|HEI Rack AD/DA (OLGMADDA)]] - <span style="color:#A02020">[''Deprecated'']</span><br />
* [[Hardware/FPGARackZynqADDAV1|HEI Rack Zynq AD/DA (ZynqADDA)]]<br />
* [[Hardware/FPGARackHiSADDAV1|HEI Rack Hi-Speed AD/DA (HiSADDA)]]<br />
* [[Hardware/FPGARackRelayCtrlV1|HEI Rack Relay Ctrl]]<br />
* [[Hardware/HEIRackRF|HEI Rack RF]]<br />
<br />
== Mezzanine Boards ==<br />
* [[Hardware/Mezzanine/Ethertap|EBS Mezza Parallel I/O and Ethernet tap]]<br />
* [[Hardware/Mezzanine/ADC|EBS Mezza 8-channel ADC]]<br />
* [[Hardware/Mezzanine/high-speed AD-DA|EBS Mezza high-speed AD-DA]] - <span style="color:#A02020">[''Deprecated'']</span><br />
* [[Hardware/Mezzanine/audio AD-DA|EBS Mezza audio AD-DA]]<br />
* [[Hardware/Mezzanine/PWM|EBS Mezza PWM]]<br />
<br />
== Extension Boards == <br />
* [[Hardware/Extention/Passive_Ethertap|HES-SO Passive Ethernet Measurement Point]]<br />
<br />
== Parallelport Boards ==<br />
Boards with a Paralellport connector compatible with the [[Hardware/FPGAEBS|FPGA EBS]] board.<br />
<br />
* [[Hardware/Parallelport/motor|EBS Motor (Clock)]]<br />
* [[Hardware/Parallelport/PTP|PTP]]<br />
* [[Hardware/Parallelport/DAC2|2-channel DAC]]<br />
* [[Hardware/Parallelport/heb_gia|GIA (Generic Inverting Amplifier)]]<br />
* [[Hardware/Parallelport/Audio_ADC_DAC|Audio ADC DAC]]<br />
<br />
=== HEB ===<br />
<br />
'''H'''EI '''E'''ducational '''B'''oards feature a well defined form factor with a Paralellport connector compatible with the [[Hardware/FPGAEBS|FPGA EBS]] board and defined holes for mounting.<br />
<br />
* [[Hardware/Parallelport/heb_lcd|LCD (with 4 buttons and 8 LEDs)]]<br />
* [[Hardware/Parallelport/heb_rotary|4 rotary switches]]<br />
* [[Hardware/Parallelport/heb_synchro|Synchro]]<br />
* [[Hardware/Parallelport/heb_microphone|Beeper and microphone]]<br />
* [[Hardware/Parallelport/heb_jtag|JTAG and RS232]]<br />
* [[Hardware/Parallelport/heb_rs232|RS232]]<br />
* [[Hardware/Parallelport/heb_matrix|7 x 10 LED matrix]]<br />
<br />
== Sensor Boards ==<br />
=== SmartHome ===<br />
* [[Hardware/Develco/index|Develco Products]]<br />
=== GPS ===<br />
* [[Hardware/Sensor/GPS_Navman|Navman Jupiter30]]<br />
=== Acceleration ===<br />
* [[Hardware/Sensor/JoyWarrior J24F14|JoyWarrior JW24F14]]<br />
=== Environment ===<br />
* [http://wiki.hevs.ch/fsi/index.php5/HiRel/CanSat/Slave_Sensors CanSat Slave Sensor (Humidity, Temperature, Pression) ]<br />
<br />
== Programmers / Interfaces ==<br />
* [[Hardware/Programmers|FPGA Programmers]]<br />
* [[Hardware/Interfaces|USB to CAN Interface]]<br />
<br />
== Buses ==<br />
* [[Hardware/Bus/i2c| i2c]]<br />
[[Category:Hardware]]</div>
Tristan.renon