Components/Libraries/VHDL/SPI

The toplevel block spiFIFO provides a SPI interface and two FIFO interface. The Slave FIFO interface makes the received data on during a write Transfer accessible. The Master FIFO interface serves as buffer for data to send on the SPI line.

Blocks

spiFIFO

Toplevel bloc

spiTransceiver

Low Level SPI bloc

spiTimer

Generates en signal for sending frame and SPI_clk

spiWrite

sends data written on the FIFO interface to the Transceiver

Depends on

• Common
• Memory

Is used by

• <none>

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