The toplevel block
spiFIFO provides a SPI interface and two FIFO interface.
The Slave FIFO interface makes the received data on during a write Transfer accessible.
The Master FIFO interface serves as buffer for data to send on the SPI line.
- Toplevel bloc
- Low Level SPI bloc
- Generates en signal for sending frame and SPI_clk
- sends data written on the FIFO interface to the Transceiver
Is used by