File:FPGA Mezza ADC.jpg
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HES-SO FPGA-EBS ADC Mezzanine
File history
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| Date/Time | Thumbnail | Dimensions | User | Comment | |
|---|---|---|---|---|---|
| current | 16:13, 17 August 2012 | | 1,600 × 1,275 (255 KB) | Zas (Talk | contribs) | (Reverted to version as of 14:12, 17 August 2012) |
| 16:13, 17 August 2012 |  | 1,600 × 1,275 (255 KB) | Zas (Talk | contribs) | (Mezzanine FPGA Board with 4 ADC Channels.) | |
| 16:12, 17 August 2012 |  | 1,600 × 1,275 (255 KB) | Zas (Talk | contribs) | (Mezzanine FPGA Board with 4 ADC Channels.) | |
| 14:04, 8 March 2012 |  | 1,600 × 1,275 (146 KB) | Zas (Talk | contribs) | (HES-SO FPGA-EBS ADC Mezzanine) |
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