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  • The mezzanine board has four 3.5mm jack input connectors. ...df|FPGA ADC Mezza Schematic PDF]] || 8 Channel (4 * Stereo Jack input) ADC Mezzanine Extension. It uses the [[Media:ADC_Cirrus_CS5368.pdf|Cirrus Logic CS5368 AD
    763 B (108 words) - 07:49, 22 January 2013
  • | V1.0 || [[File:FPGA_Mezza_Ethernettap.jpg|200px|Ethernettap Mezzanine]] || [[Media:FPGA_Mezza_Ethernettap_schematic.pdf|FPGA Ethernettap Mezza Sc [[Category:Hardware]][[Category:Mezzanine]]
    1 KB (148 words) - 06:25, 22 February 2013
  • == High-speed AD/DA mezzanine board == [[File:FPGA_Mezza_Highspeed_ADDA.jpg|200px|Highspeed AD-DA Mezzanine]]
    621 B (81 words) - 14:50, 7 November 2016
  • == Audio AD/DA mezzanine board == [[File:FPGA_Mezza_Audio_ADDA.jpg|200px|Audio AD-DA Mezzanine]]
    2 KB (329 words) - 06:51, 7 November 2012
  • [[Category:Hardware]] [[Category:Mezzanine]] [[Category:HEB]]
    441 B (60 words) - 13:13, 18 January 2018
  • This mezzanine was developped for the FPGA Poetic Board during [https://gitlab.hevs.ch/the The mezzanine board has 8 SMA connectors (DAC output), 2 connectors 2x10 pins (ADC input)
    1 KB (152 words) - 12:00, 1 October 2021

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  • == Mezzanine Boards == * [[Hardware/Mezzanine/Ethertap|EBS Mezza Parallel I/O and Ethernet tap]]
    6 KB (745 words) - 09:23, 6 September 2022
  • ! Type || FPGA-EBS Full board || FPGA-EBS Student board || FPGA-EBS Mezzanine || Schematic || UCF || Description ...:FPGA_Mezza_v2_1.jpg|115px|FPGA EBS Mezza V2.1]] [[Hardware/Stock_FPGA-EBS#Mezzanine|boards 40-41]] || [[Media:FPGA_EBS_v2_1_schematics.pdf|PDF]] || [[Media:FP
    4 KB (653 words) - 07:25, 10 March 2020
  • {{WarningBox|content=Mezzanine Pin <code>T8</code> - <code>MEZ_PB19</code> can't be used if a ''XC6SLX100' * 2 Mezzanine Connector ARM-EBS and FPGA-EBS compatible
    2 KB (393 words) - 12:08, 5 April 2017
  • ** Mezzanine system : * VIDEO mezzanine : controller with SVGA capabilities
    2 KB (229 words) - 12:41, 26 June 2015
  • '''Our Hardware stock is placed in A201 and A309. If you take some Mezzanine Boards please change the location of the board you took in the appropriate == [[Hardware/Mezzanine/Ethertap|Ethernet Tap]] ==
    4 KB (310 words) - 11:07, 17 October 2019
  • ...DAC has been used together with 2 [[Hardware/ADC/AD7760|AD7760 ADCs]] on a mezzanine board used for the MOLIS and IGOR projects.
    539 B (86 words) - 07:42, 7 September 2012
  • ...een used together with a [[Hardware/DAC/AD5547|AD5547 2-outputs DAC]] on a mezzanine board used for the MOLIS and IGOR projects.
    449 B (71 words) - 07:42, 7 September 2012
  • The mezzanine board has four 3.5mm jack input connectors. ...df|FPGA ADC Mezza Schematic PDF]] || 8 Channel (4 * Stereo Jack input) ADC Mezzanine Extension. It uses the [[Media:ADC_Cirrus_CS5368.pdf|Cirrus Logic CS5368 AD
    763 B (108 words) - 07:49, 22 January 2013
  • | V1.0 || [[File:FPGA_Mezza_Ethernettap.jpg|200px|Ethernettap Mezzanine]] || [[Media:FPGA_Mezza_Ethernettap_schematic.pdf|FPGA Ethernettap Mezza Sc [[Category:Hardware]][[Category:Mezzanine]]
    1 KB (148 words) - 06:25, 22 February 2013
  • == High-speed AD/DA mezzanine board == [[File:FPGA_Mezza_Highspeed_ADDA.jpg|200px|Highspeed AD-DA Mezzanine]]
    621 B (81 words) - 14:50, 7 November 2016
  • == Audio AD/DA mezzanine board == [[File:FPGA_Mezza_Audio_ADDA.jpg|200px|Audio AD-DA Mezzanine]]
    2 KB (329 words) - 06:51, 7 November 2012
  • * [[Hardware/Stock_Mez|Mezzanine]]
    2 KB (266 words) - 08:29, 5 April 2021
  • * 2 50Pin HESSO Mezzanine connection (compatible with FPGA-EBS, FPGA-Rack, ARM-EBS) * Power Supply through connector or Mezzanine
    2 KB (259 words) - 07:53, 20 September 2013
  • ...ce FPGA|up=Inventory|up_name=Inventory|right=Hardware/Stock_Mez|right_name=Mezzanine}}
    2 KB (171 words) - 09:51, 27 November 2017
  • * added connector for AudioAmp Mezzanine Input {{navNamed|left=Hardware/Stock_Mez|left_name=Mezzanine|up=Inventory|up_name=Inventory|right=Hardware/Stock_Backplane|right_name=Ra
    15 KB (863 words) - 09:14, 6 December 2019
  • * Connect Mezzanine Audio Adapter board * Power the FPGA via the Mezzanine connector
    2 KB (376 words) - 06:35, 21 August 2014
  • Currently there exist two setups, one with about 2 cm between the mezzanine and the cover and the other one with about 6.5 cm. If the sensor needs anot ...ith other levels, a level translation circuit has to be implemented on the mezzanine board.
    7 KB (1,087 words) - 15:26, 31 July 2017
  • {{WarningBox|content=Mezzanine Pin <code>T8</code> - <code>MEZ_PB19</code> can't be used if a ''XC6SLX100' * 2 Mezzanine Connector ARM-EBS and FPGA-EBS compatible
    5 KB (731 words) - 10:42, 12 December 2016
  • [[Category:Hardware]] [[Category:Mezzanine]] [[Category:HEB]]
    441 B (60 words) - 13:13, 18 January 2018
  • ...e]]. Additional specific hardware can be connected to HiRADDA as stackable mezzanine card.
    9 KB (1,395 words) - 09:20, 28 March 2018

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