Components/Designs/VHDL template

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(Created page with "{{TOC right}} There is a template VHDL Design available where most used IP Cores developed by HES-SO Valais are included. If you need to start a new project and you need a VH...")
 
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# Checkout SVN Repository
 
# Checkout SVN Repository
 
# Check project folder (eln_board, fpga_rack) and modify hdlDesigner.bat start script.
 
# Check project folder (eln_board, fpga_rack) and modify hdlDesigner.bat start script.
#:<pre> VHDL/eln_board/hdlDesigner </pre>
+
#:<pre> VHDL/eln_board/hdlDesigner.bat </pre>
 
# DONE
 
# DONE
  

Revision as of 08:34, 13 June 2012

Contents

There is a template VHDL Design available where most used IP Cores developed by HES-SO Valais are included. If you need to start a new project and you need a VHDL Design to start with, this is the place.

The following pages explains how this design is build and can be reused for a different project.

SVN Repository

You can find the Template VHDL Design in our SVN Repository.

Programs

The Design is done with the following tools:

  • HDL-Designer 2009.2
  • Mentor Modelsim 6.6
  • Xilinx ISE 12.1

The Tools in Bold are important and should be kept

Directory Structure

└───VHDL                                   -- Design main folder
    ├───eln_board                          -- Project folder for ELN_board testing
    │   ├───Board                          -- Board Toplevel design (with Synchronisation)
    │   │   ├───concat                     -- Generated concat VHDL & UCF file
    │   │   ├───hdl
    │   │   ├───hds
    │   │   └───ise                        -- ISE Project file
    │   ├───BoardTester                    -- Board Toplevel design (without Synchronisation)
    │   │   ├───hdl
    │   │   └───hds
    │   ├───BoardTester_test               -- Testbench for BoardTester
    │   │   ├───hdl
    │   │   └───hds
    │   ├───Prefs                          -- HDL Designer Prefs for Project ELN_Board
    │   │   ├───dc_user
    │   │   ├───dp_user
    │   │   ├───hds_team
    │   │   ├───hds_user
    │   │   └───hds_user-linux
    │   └───Simulation                     -- Folder for Sim File e.g. *.do, *.eth, *.txt, *.srec
    ├───fgpa_rack                          -- Project folder for FPGA_Rack testing
    │   ├───Board                          -- Board Toplevel design (with Synchronisation)
    │   │   ├───concat                     -- Generated concat VHDL & UCF file
    │   │   ├───hdl
    │   │   ├───hds
    │   │   └───ise                        -- ISE Project file
    │   ├───BoardTester                    -- Board Toplevel design (without Synchronisation)
    │   │   ├───hdl
    │   │   └───hds
    │   ├───BoardTester_test               -- Testbench for BoardTester
    │   │   ├───hdl
    │   │   └───hds
    │   ├───Prefs                          -- HDL Designer Prefs for Project FPGA_Rack
    │   │   ├───dc_user
    │   │   ├───dp_user
    │   │   ├───hds_team
    │   │   ├───hds_user
    │   │   └───hds_user-linux
    │   └───Simulation                     -- Folder for Sim File e.g. *.do, *.eth, *.txt, *.srec
    └───libs                               -- Folder for all NON-Project specific libraries
        ├───CommandLine                    -- Library Commandline for Commandline parsing
        │   ├───hdl
        │   └───hds
        ├───CommandLine_test               -- Testbench for Library Commandline
        │   ├───hdl
        │   └───hds
        ├───Common                         -- Library Common with useful packages
        │   ├───hdl
        │   └───hds
        ├───Common_test                    -- Testbench for Library Common
        │   ├───hdl
        │   └───hds
        ├───Cordic                         -- Library Cordic for Sinus / Cosinus generator
        │   ├───hdl
        │   └───hds
        ├───Cordic_test                    -- Testbench for Library Cordic
        │   ├───hdl
        │   └───hds
        ├───Ethernet                       -- Library Ethernet for 100Mbps Transceiver
        │   ├───hdl
        │   └───hds
        ├───Ethernet_test                  -- Testbench for Library Ethernet
        │   ├───hdl
        │   └───hds
        ├───I2C                            -- Library I2C for I2C commmunication
        │   ├───hdl
        │   └───hds
        ├───I2C_test                       -- Testbench for Library I2C
        │   ├───hdl
        │   └───hds
        ├───Memory                         -- Library Memory for BRAM, FIFO, SDRAM Controller, Flash Controller
        │   ├───hdl
        │   └───hds
        ├───Memory_test                    -- Testbench for Library Memory
        │   ├───hdl
        │   └───hds
        ├───RS232                          -- Library RS232 for RS232 Communication
        │   ├───hdl
        │   └───hds
        └───RS232_test                     -- Testbench for Library RS232
            ├───hdl
            └───hds

Project Files

There are multiple level of "Project Files".

hdldesigner.bat

This file is specific to each project and can be found in the Project folder e.g. VHDL/eln_board/hdlDesigner.bat It does the following:

  • Define environment variables used
    • by HDL-Designer
    • by the project
  • Prepare SCRATCH_DIR for intermediate files
    • Create SCRATCH_DIR
    • Copy ISE Designfiles into it
  • Launch HDL-Designer

hds.hdp

This file is specific to each project and can be found in the Prefs folder inside the Project folder e.g. VHDL/eln_board/Prefs/hds.hdp It contains:

  • Location of all HDL-Designer libraries

This file has multiple sections

Section Description
[Concat] Defines location of the Concatenation folder. Only needed for the Board library
[Modelsim] Defines location of the Modelsim work folder.
[hdl] Defines location of the hdl folder. For storing all pure *.vhd files
[hds] Defines location of the hds folder. For storing all HDL-Designer Design files such as Statemachines, Designblocs and other Graphical files.
[hds_settings] Defines the Design roots marker of libraries.
[library_type] Defines library types (regular, standard)
[shared] Defines Shared libraries

Using the Project

As "it is"

  1. Checkout SVN Repository
  2. Check project folder (eln_board, fpga_rack) and modify hdlDesigner.bat start script.
     VHDL/eln_board/hdlDesigner.bat 
  3. DONE

As Template

  1. Checkout SVN Repository
  2. Generate you own project folder under VHDL/
     VHDL/projectname 
  3. Copy needed filed and folder from example project (eln_board or fpga_rack)
    Copy eln_board content to your project folder
        ├───eln_board                          -- Project folder for ELN_board testing
        │   ├───Board                          -- Board Toplevel design (with Synchronisation)
        │   │   ├───concat                     -- Generated concat VHDL & UCF file
        │   │   ├───hdl
        │   │   ├───hds
        │   │   └───ise                        -- ISE Project file
        │   ├───BoardTester                    -- Board Toplevel design (without Synchronisation)
        │   │   ├───hdl
        │   │   └───hds
        │   ├───BoardTester_test               -- Testbench for BoardTester
        │   │   ├───hdl
        │   │   └───hds
        │   ├───Prefs                          -- HDL Designer Prefs for Project
        │   │   ├───dc_user
        │   │   ├───dp_user
        │   │   ├───hds_team
        │   │   ├───hds_user
        │   │   └───hds_user-linux
        │   └───Simulation                     -- Folder for Sim File e.g. *.do, *.eth, *.txt, *.srec
  4. Modify hdlDesigner.bat in your projectfolder.
  5. Start HDLDesigner
  6. Delete and Create your own Design in BoardTester Library
  7. Delete and Create your own Toplevel Design in Board Library
  8. Delete and Create your own Testbench in BoardTester_test
  9. Delete and add you own Simulation files if needed, store you waveform files also here
  10. DONE
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