Components/Ethernet/IPs/UDP FIFO

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(Created page with "{{TOC right}} == UDP FIFO == The Ethernet UDP FIFO core connects to the MII to dual port RAM interface on one side and provides a FIFO p...")
 
(Testing)
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== Testing ==
 
== Testing ==
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=== Bonjour ===
  
 
Each FPGA board has a unique MAC address, as [[Standards/Ethernet/MAC_addresses#HES-SO_MAC_adresses|specified by UIT]].
 
Each FPGA board has a unique MAC address, as [[Standards/Ethernet/MAC_addresses#HES-SO_MAC_adresses|specified by UIT]].
 
The [http://en.wikipedia.org/wiki/Bonjour_(software) bonjour] name of the board is <code>fpga<i>nn</i></code>,
 
The [http://en.wikipedia.org/wiki/Bonjour_(software) bonjour] name of the board is <code>fpga<i>nn</i></code>,
 
where <code><i>nn</i></code> is the FPGA board id.
 
where <code><i>nn</i></code> is the FPGA board id.
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Open [http://www.wireshark.org/ Wireshark] and filter [[Standards/Ethernet/Bonjour|bonjour]] protocol:
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ip.version==4 and udp.port==5353
  
 
Find the board's IP address:
 
Find the board's IP address:
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The board won't answer the <code>ping</code>,
 
The board won't answer the <code>ping</code>,
 
but the terminal will show the board's IP address as found with the help of <code>bonjour</code>.
 
but the terminal will show the board's IP address as found with the help of <code>bonjour</code>.
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=== Discard ===
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Trigger on the [http://en.wikipedia.org/wiki/Discard_Protocol discard protocol]:
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udp.port==9
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On the FPGA board, press on the button connected to the discard protocol block.
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In Wireshark, check for the frame being sent.
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[[Category:Components]] [[Category:Designs]] [[Category:VHDL]] [[Category:IP]]
 
[[Category:Components]] [[Category:Designs]] [[Category:VHDL]] [[Category:IP]]

Revision as of 17:03, 22 September 2014

Contents

UDP FIFO

The Ethernet UDP FIFO core connects to the MII to dual port RAM interface on one side and provides a FIFO port on the other one.

On the receiver side, it:

  • checks the MAC address (supports multicast) and trims the Ethernet header away
  • checks the IP address (supports multicast and broadcast) and trims the IP header away
  • trims the UDP header
  • writes the payload data into a FIFO

On the sender side side, it:

  • reads the payload data from a FIFO
  • adds an UDP header
  • adds an IP header
  • adds an Ethernet header

As ports to the core, MAC and IP addresses come in 3 flavours:

  • the FPGA's address
  • the incoming frame's address
  • the outgoing frame's address

UDP components

On the application side, a basic development system provides the following UDP blocks:

Additionally:

  • a kind of demultiplexer transmits the input FIFO controls to the block selected by the UDP port number
  • a kind of multiplexer sends data from any given block to the output FIFO

The blocks have to register their port number to the demultiplexer. If no block corresponds to the incoming UDP frame, the demultiplexer empties the input FIFO. The blocks have to ask for write access to the output FIFO. Access is granted on a priority based on the component indexes.

Testing

Bonjour

Each FPGA board has a unique MAC address, as specified by UIT. The bonjour name of the board is fpgann, where nn is the FPGA board id.

Open Wireshark and filter bonjour protocol:

ip.version==4 and udp.port==5353

Find the board's IP address:

ping fpga30.local

The board won't answer the ping, but the terminal will show the board's IP address as found with the help of bonjour.

Discard

Trigger on the discard protocol:

udp.port==9

On the FPGA board, press on the button connected to the discard protocol block. In Wireshark, check for the frame being sent.

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