Components/Ethernet/IPs/UDP FIFO

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The Ethernet UDP FIFO core connects to the MII to dual port RAM interface on one side and provides a FIFO port on the other one.

On the receiver side, it:

  • checks the MAC address (supports multicast) and trims the Ethernet header away
  • checks the IP address (supports multicast and broadcast) and trims the IP header away
  • trims the UDP header
  • writes the payload data into a FIFO

On the sender side side, it:

  • reads the payload data from a FIFO
  • adds an UDP header
  • adds an IP header
  • adds an Ethernet header

As ports to the core, MAC and IP addresses come in 3 flavours:

  • the FPGA's address
  • the incoming frame's address
  • the outgoing frame's address

UDP components

On the application side, a basic development system provides the following UDP blocks:


  • a kind of demultiplexer transmits the input FIFO controls to the block selected by the UDP port number
  • a kind of multiplexer sends data from any given block to the output FIFO

The blocks have to register their port number to the demultiplexer. If no block corresponds to the incoming UDP frame, the demultiplexer empties the input FIFO. The blocks have to ask for write access to the output FIFO. Access is granted on a priority based on the component indexes.


Each FPGA board has a unique MAC address, as specified by UIT. The bonjour name of the board is fpgann, where nn is the FPGA board id.

Find the board's IP address:

ping fpga30.local

The board won't answer the ping, but the terminal will show the board's IP address as found with the help of bonjour.

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