Revision as of 17:43, 31 October 2016

The NanoBlaze is a grow-up of the Xilinx PicoBlaze microprocessor, hence the name. The PicoBlaze is a simple, orthogonal RISC Von Neumann processor which has raised a large interest and pushed developers to design several device independant variants.

This processor is used in our embedded systems course lab, together with an I/O space to AHB-Lite adapter. It processes each instruction, except for the jumps, within a single clock period.

The interrupt logic has not been implemented yet.

Component

The figure on the right shown the processor's inputs and outputs.

Generics

Various sizes can be defined with the help of generic parameters:

• registerBitNb defines the data bit width
• registerAddressBitNb allows to choose the number of internal registers
• programCounterBitNb allows to cope with different program lengths
• stackPointerBitNb adapts to various nesting depths of the subroutines
• scratchPadAddressBitNb allows to manage the size of the scratchpad
• addressBitNb defines the size of the I/O space

With scratchPadAddressBitNb = 0, the scratchpad is not implemented physically.

Pipeline

Contrarily to the PicoBlaze, the NanoBlaze executes every instruction within a single clock cycle. This design choice reduces the maximal operating speed compared to the original pipelined processor. However, an additional en input allows to have it work at half the clock rate and so catch up the performance of the original processor, as long as the synthesis tool allows to do so. Dividing the operating frequency by a factor greater than 2 allows the NanoBlaze to work in systems working at even higher frequencies without requiring to split a design into multiple clock domains.

Synchronous BlockRam delay

The NanoBlaze's instruction ROM is designed to be mapped as a Block RAM. Due to this mapping, the instructions are provided delayed by one clock period compared to the program counter. With this, when a branch condition is met, the processor will anyway have received the instruction of the next memory location. Obviously, that instruction will not be executed, and this means that every successful branch requires two clock cycles.

Assembler

The NanoBlaze has an assembler written in PERL which thus runs on any operating system. In our labs, the assembler is integrated in the Mentor HDL Designer environment.

The VHDL processor code includes a disassembler VHDL process which translates the current instruction in the form of a string. This string can be displayed in the simulator for debugging purpose. The corresponding VHDL code is commented out for synthesis via the pragma translate_off clause.

Instruction set

The following table shows the instruction set in the case of an 8 bit processor with 16 registers and 10 program address bits:

The length of the instruction is adapted to cope with the different generic values associated to the component.

Sources

This IP is found in the HEVs EDA Repository: svn: https://repos.hevs.ch/svn/eda/