Hardware/CubeSat Gumstix

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The connection to the FPGA is given in the following table:
 
The connection to the FPGA is given in the following table:
 +
{| class="wikitable" style="margin: 20pt"
 +
! ADC<br />signal || FPGA<br />pin || function
 +
|-
 +
| CS_n || C16 || chip select, active low
 +
|-
 +
| SCLK || B12 || serial clock
 +
|-
 +
| DOUT || A18 || slave out (MISO)
 +
|-
 +
| DIN || C17 || slave in (MOSI)
 +
|-
 +
| PD_n_RST_n || B18 || power down or restart, active low
 +
|-
 +
| BUSY || A17 || busy aquiring temperature
 +
|}
 +
 +
== Gumstix ==
 +
 +
A gumstix board can be plugged on the CubeSat board.
 +
 +
The SPI link to the FPGA is given in the following table:
 
{| class="wikitable" style="margin: 20pt"
 
{| class="wikitable" style="margin: 20pt"
 
! ADC<br />signal || FPGA<br />pin || function
 
! ADC<br />signal || FPGA<br />pin || function

Revision as of 15:36, 9 October 2015

Contents

This board is the result of a diploma work. It is meant to be a first evaluation version of a Cubesat image processing board.

Type FPGA Rack Schematic UCF Description
2015 FPGA + Gumstix 2015 FPGA + Gumstix 2015 schematic

top view
FPGA + Gumstix 2015 UCF FPGAs: Spartan 6 XC6SLX45, XC6SLX100 or XC6SLX150

SPI flash: M23P64-ME

Components

Camera

The camera interface connector is foreseen to be used with different camera models. The connector layout is:

connector
pin
signal FPGA
pin
function
1 3.3 V power supply
2 GND
3 TxD / SCLK A4 RS232 / I2C control
4 RxD / SDA B10
5 Frame valid / VSync A5 frame control
6 Line valid / HRef C5
7 Data valid B6
8 Pixel clock A10
9 D0 A6 frame data
10 D1 D6
11 D2 A7
12 D3 C6
13 D4 B8
14 D5 C7
15 D6 A8
16 D7 D8
17 D8 A9
18 D9 C8
19 D10 A13
20 D11 C9
21 CC1 / ExtSync A14 camera control
22 CC2 / XCLK C14
23 CC3 / Reset B14
24 CC4 / PowerDn D14

ADC

The board hosts a ADS8028 12-bit, 1 MSPS, 8-channel analog-to-digital converter.

The ADC is powered with the input 5 V for the analog part and with a local 3.3 V for the digital lines. The voltage reference input connects to the analog power supply via jumper J5.

Inputs AIN0 to AIN4 are used to monitor the board's power supplies. Inputs AIN5 to AIN7 are sourced by connector J9.

The connection to the FPGA is given in the following table:

ADC
signal
FPGA
pin
function
CS_n C16 chip select, active low
SCLK B12 serial clock
DOUT A18 slave out (MISO)
DIN C17 slave in (MOSI)
PD_n_RST_n B18 power down or restart, active low
BUSY A17 busy aquiring temperature

Gumstix

A gumstix board can be plugged on the CubeSat board.

The SPI link to the FPGA is given in the following table:

ADC
signal
FPGA
pin
function
CS_n C16 chip select, active low
SCLK B12 serial clock
DOUT A18 slave out (MISO)
DIN C17 slave in (MOSI)
PD_n_RST_n B18 power down or restart, active low
BUSY A17 busy aquiring temperature

Peripheral connectors

Two 24-pin peripheral connectors are provided. Both comprise 2 power supply pins and 22 FPGA I/O:

connector
pin
FPGA pin
peripheral 1
FPGA pin
peripheral 2
1 3.3 V 3.3 v
2 GND GND
3 Y1 L1
4 Y2 L3
5 W1 K1
6 W3 K3
7 V1 J1
8 V3 J3
9 U1 H1
10 U3 H3
11 T2 H2
12 T4 H4
13 T1 G1
14 T3 G4
15 R1 F1
16 R4 F3
17 P1 F2
18 R3 F5
19 N1 E1
20 N3 E3
21 M2 D1
22 M4 D3
23 M1 D2
24 M3 D5

Power supplies

The board receives a 5 V power input. 4 DC/DC converters provide power for different components.

FPGA supply

On the FPGA:

  • VCC33 is used by the FPGA for VCCAUX, the SPI flash, the JTAG connector, bank 0 and bank 3
  • VCC18/33 is used for FPGA bank 1
  • VCC25/33 is used for FPGA bank 2
  • VCC12 is used for the FPGA core

Bank 0 connects to the camera and the ADC

Bank 1 is connected to the Gumstix and 1.8 V should be used. The Gumstix board could be replaced by a memory board which might require 3.3 V signalling

Bank 2 connects to the On-Board Computer (OBC). The OBC connector B allows to have SpaceWire differential lines. If so, one has to mount the 165 Ω serial and 140 Ω parallel resistors. Normal CMOS signalling requires 0 Ω serial and no parallel resistors.

Bank 3 connects to the spare connectors on the side of the board.

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