Revision as of 18:09, 23 September 2013

General

After designing and simulating your design based on VHDL Template Design, you have to prepare it:

1. In HDL-Designer: Perform Task Flow Prepare for Synthesis
   1. Generates all VHDL Files
   2. Concatenates them into a single VHDL File
   3. Trims work libraries
2. In HDL-Designer: Perform Task Flow Xilinx Project Navigator
   1. Updates the ISE (*.xise) Project file
   2. Launches ISE
3. In ISE: Perform Task Generate Programming File
   1. Runs Synthesis
   2. Runs P&R
   3. Generate Programming File *.bit
4. In ISE: Perform Task Configure Target Device
   1. Launches Impact

After that you can either way download the file directly to the FPGA or create another file to download to the non-volatile memory.

FPGA Configuration

Flash Writing