Hardware/FPGAPoetic

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! Type || FPGA Rack || Schematic || UCF || Description
 
! Type || FPGA Rack || Schematic || UCF || Description
 
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| V1.0 || [[File:FPGA_Rack_v1_0.jpg|200px|FPGA Rack V1.0]] || [[Media:FPGARack_v1_0_schematics.pdf|FPGA-Rack v1.0 Schematic PDF]] || [[Media:FPGARack_v1_0.ucf|FPGA-Rack v1.0 UCF Files]] || There are different FPGA mounted: Spartan 6 XC6SLX45, Spartan 6 XC6SLX100, Spartan 6 XC6SLX150
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| V1.0 || [[File:FPGA_Poetic_v1_0.png|200px|FPGA Poetic V1.0]] || [[Media:FPGAPoetic_v1_0_schematics.pdf|FPGA-Poetic v1.0 Schematic PDF]] || [[Media:FPGARack_v1_0.ucf|FPGA-Rack v1.0 UCF Files]] || There are different FPGA mounted: Spartan 6 XC6SLX45, Spartan 6 XC6SLX100, Spartan 6 XC6SLX150
 
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Revision as of 12:25, 1 October 2021

Contents

The basic idea behind this board is to have a development FPGA board, with a choice of big FPGA's and a VME compatible 2U Rack connector. The stock can be verified and updated on-line.

Type FPGA Rack Schematic UCF Description
V1.0 FPGA Poetic V1.0 FPGA-Poetic v1.0 Schematic PDF FPGA-Rack v1.0 UCF Files There are different FPGA mounted: Spartan 6 XC6SLX45, Spartan 6 XC6SLX100, Spartan 6 XC6SLX150

The boards are compatible with the FPGA Rack Backplane for interconnecting different boards with the help of the HES-SO Backplane Bus and the HES-SO VME IP Core.

A VHDL test code with the default UCF Files can be found at the EDA SVN Repository:

Features

  • 1 Ethernet Port
  • USB FTDI
  • Spartan 6 LX45 - LX100 - LX150
  • 2x4 Leds
  • 4 User Switches
  • 3 Buttons
  • 106.25MHz Main Clock
  • VME connector 3x32Pin compatible with POETIC Rack backplane
  • 2 Mezzanine Connector ARM-EBS and FPGA-EBS compatible
  • Powered by USB or VME Power

Programmation

V1.0 is only programmable via JTAG.

Links

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