Hardware/FPGAPoetic

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The basic idea behind this board is to have a development FPGA board, with a choice of big FPGA's and a VME compatible 2U Rack connector. The [[Hardware/Stock_FPGA-Rack|stock]] can be verified and updated on-line.
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The basic idea behind this board is to have a FPGA board that interface a VME connector compatible with the POETIC Rack backplane.
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This board was developped during [https://gitlab.hevs.ch/theses/bachelor/jean-nanchen/fpga-developing-board-demonstrator Jean Nanchen's TB] (2021) and used in the NGRW project in addition with the [[Hardware/Mezzanine/Poetic|FPGA ADC-DAC Mezzanine]].
  
 
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! Type || FPGA Poetic || Schematic || UCF || Description
 
! Type || FPGA Poetic || Schematic || UCF || Description
 
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| V1.0 || [[File:FPGA_Poetic_v1_0.png|200px|FPGA Poetic V1.0]] || [[Media:FPGAPoetic_v1_0_schematics.pdf|FPGA-Poetic v1.0 Schematic PDF]] || [[Media:FPGARack_v1_0.ucf|FPGA-Rack v1.0 UCF Files]] || There are different FPGA mounted: Spartan 6 XC6SLX45, Spartan 6 XC6SLX100, Spartan 6 XC6SLX150
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| V1.0 || [[File:FpgaPoetic.png|200px|FPGA Poetic V1.0]] || [[Media:FPGAPoetic_v1_0_schematics.pdf|FPGA-Poetic v1.0 Schematic PDF]] || [[Media:FPGARack_v1_0.ucf|FPGA-Rack v1.0 UCF Files]] || There are different FPGA mounted: Spartan 6 XC6SLX45, Spartan 6 XC6SLX100, Spartan 6 XC6SLX150
 
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The boards are compatible with the [[Hardware/FPGARackBackplane|FPGA Rack Backplane]] for interconnecting different boards with the help of the [[Standards/HEI_'VME'_Backplane_Bus|HES-SO Backplane Bus]] and the [[Components/IP/VME|HES-SO VME IP Core]].
 
 
A VHDL test code with the default UCF Files can be found at the EDA SVN Repository:
 
* https://repos.hevs.ch/svn/eda/VHDL/fgpa_rack
 
  
 
= Features =
 
= Features =
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* 2 Mezzanine Connector ARM-EBS and FPGA-EBS compatible
 
* 2 Mezzanine Connector ARM-EBS and FPGA-EBS compatible
 
* Powered by USB or VME Power
 
* Powered by USB or VME Power
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= Analog to digital converters =
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The mezzanine board holds 20 [https://www.ti.com/product/ADS7886 ADS7886] analog to digital converters.
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These are 12 bit converters with a maximal sampling rate of 1 MHz.
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= Digital to analog converters =
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The mezzanine board holds 2 [https://www.ti.com/product/DAC124S085 DAC124S085] quad analog to digital converters,
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allowing for 8 analog output channels.
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These are quad 12 bit converters with a maximal sampling rate of 1.8 MHz if only one channel is used.
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The sampling rate drops to 460 kHz when all 4 channels are used.
  
 
= Programmation =
 
= Programmation =

Revision as of 09:28, 22 November 2021

Contents

The basic idea behind this board is to have a FPGA board that interface a VME connector compatible with the POETIC Rack backplane. This board was developped during Jean Nanchen's TB (2021) and used in the NGRW project in addition with the FPGA ADC-DAC Mezzanine.

Type FPGA Poetic Schematic UCF Description
V1.0 FPGA Poetic V1.0 FPGA-Poetic v1.0 Schematic PDF FPGA-Rack v1.0 UCF Files There are different FPGA mounted: Spartan 6 XC6SLX45, Spartan 6 XC6SLX100, Spartan 6 XC6SLX150


Features

  • 1 Ethernet Port
  • USB FTDI
  • Spartan 6 LX45 - LX100 - LX150
  • 2x4 Leds
  • 4 User Switches
  • 3 Buttons
  • 106.25MHz Main Clock
  • VME connector 3x32Pin compatible with POETIC Rack backplane
  • 2 Mezzanine Connector ARM-EBS and FPGA-EBS compatible
  • Powered by USB or VME Power

Analog to digital converters

The mezzanine board holds 20 ADS7886 analog to digital converters.

These are 12 bit converters with a maximal sampling rate of 1 MHz.

Digital to analog converters

The mezzanine board holds 2 DAC124S085 quad analog to digital converters, allowing for 8 analog output channels.

These are quad 12 bit converters with a maximal sampling rate of 1.8 MHz if only one channel is used. The sampling rate drops to 460 kHz when all 4 channels are used.

Programmation

V1.0 is only programmable via JTAG.

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