Hardware/FPGARack4ethernet

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! Type || FPGA Rack || Schematic || UCF || Description
 
! Type || FPGA Rack || Schematic || UCF || Description
 
|-
 
|-
| V1.0 || [[File:FPGA_Rack_v1_0.jpg|200px|FPGA Rack V1.0]] || [[Media:FPGARack_v1_0_schematics.pdf|FPGA-Rack v1.0 Schematic PDF]] || [[Media:FPGARack_v1_0.ucf|FPGA-Rack v1.0 UCF Files]] || There are different FPGA mounted: Spartan 6 XC6SLX45, Spartan 6 XC6SLX100, Spartan 6 XC6SLX150
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| V1.0 || [[File:FPGA Rack Ethernet4-v1 0.jpg|200px|FPGA Rack Ethernet4 V1.0]] || [[Media:FPGA Rack Ethernet4-schematics-v1 0.pdf|FPGA-Rack-Ethernet4 v1.0 Schematic PDF]] || [[Media:FPGARack_v1_0.ucf|FPGA-Rack v1.0 UCF Files]] || There are different FPGA mounted: Spartan 6 XC6SLX45, Spartan 6 XC6SLX100, Spartan 6 XC6SLX150
 
|-
 
|-
 
|}
 
|}
  
The boards are compatible with the [[Hardware/FPGARackBackplane|FPGA Rack Backplane]] for interconnecting different boards with the help of the [[Standards/HEVs_'VME'_Backplane_Bus|HES-SO Backplane Bus]] and the [[Components/IP/VME|HES-SO VME IP Core]].
+
The board is compatible with the [[Hardware/FPGARackBackplane|FPGA Rack Backplane]] for interconnecting different boards with the help of the [[Standards/HEI_'VME'_Backplane_Bus|HES-SO Backplane Bus]] and the [[Components/IP/VME|HES-SO VME IP Core]].
 +
It holds 4 Ethernet connectors, each connected to an independent [http://www.microchip.com/wwwproducts/Devices.aspx?product=KSZ8041 KSZ8041NL PHY].
 +
 
 +
= Ethernet =
 +
 
 +
== PHY clocks ==
 +
 
 +
All 4 PHYs receive the same 25 MHz clock.
 +
This clock signal can be sourced from:
 +
* the quartz oscillator closest to the PHYs (<code>CLK_PHY_25M</code>)
 +
* the FPGA (<code>CLK_PHY_FPGA</code>, pin AB13).
 +
 
 +
The FPGA can generate the PHY clock from
 +
* a 106.25 MHz quartz (<code>CLK_106_25M</code>, pin Y13)
 +
* the PHY quartz oscillator (<code>CLK_PHY_25M</code>, pin AA12)
 +
* one of the PHY Rx or Tx clocks (<code>ETHA_RX_CLK</code>, <code>ETHA_TX_CLK</code>, <code>ETHB_RX_CLK</code>, …)
 +
 
 +
The last possibility is foreseen to [https://en.wikipedia.org/wiki/Synchronous_Ethernet synchronise] the clocks of slave Ethernet ports to the one of a master port.
 +
 
 +
== Management Data Input Output (MDIO) ==
 +
 
 +
The serial [[Standards/MDI|Management Data Input Output (MDIO)]] interface is connected independently from each PHY to the FPGA.
 +
 
 +
= Serial ports =
 +
 
 +
The FPGA has 3&nbsp;serial port connections:
 +
* one via an [http://www.ftdichip.com/Products/ICs/FT232R.htm FT232RL] RS232 to USB interface (<code>USB_TXD</code>, <code>USB_RXD</code> and 6 more lines)
 +
* 2&nbsp;via a [https://datasheets.maximintegrated.com/en/ds/MAX3224E-MAX3245E.pdf level translator]
 +
** the first goes to a flat cable connector (<code>UART_TXD0</code>, <code>UART_RXD0</code>)
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** the second to the JTAG mini connector (<code>UART_TXD1</code>, <code> UART_RXD01</code>)
 +
 
 +
== USB serial interface ==
 +
 
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The [http://www.ftdichip.com/Products/ICs/FT232R.htm USB serial interface] powers the board
 +
if jumper <code>JP1</code> is set on the <code>USB_5V</code> side.
 +
 
 +
It provides a serial port and a JTAG interface.
 +
The serial port is connected directly to the FPGA.
 +
The JTAG interface can be connected to the FPGA programming lines via zero-Ohm resistors.
 +
This programming mode has not been tested yet.
 +
 
 +
= JTAG connector =
 +
 
 +
The HEI 10-pin JTAG connector provides:
 +
* a 3.3&nbsp;V power supply
 +
* 4&nbsp;JTAG signals for FPGA and Flash programmation
 +
* a minimal serial port (Rx and Tx)
 +
* 2&nbsp;FPGA I/O lines
  
 
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Latest revision as of 11:42, 12 December 2016

Contents

This board is a variant of the FPGA rack board, but with 4 Ethernet connectors.

Type FPGA Rack Schematic UCF Description
V1.0 FPGA Rack Ethernet4 V1.0 FPGA-Rack-Ethernet4 v1.0 Schematic PDF FPGA-Rack v1.0 UCF Files There are different FPGA mounted: Spartan 6 XC6SLX45, Spartan 6 XC6SLX100, Spartan 6 XC6SLX150

The board is compatible with the FPGA Rack Backplane for interconnecting different boards with the help of the HES-SO Backplane Bus and the HES-SO VME IP Core. It holds 4 Ethernet connectors, each connected to an independent KSZ8041NL PHY.

Ethernet

PHY clocks

All 4 PHYs receive the same 25 MHz clock. This clock signal can be sourced from:

  • the quartz oscillator closest to the PHYs (CLK_PHY_25M)
  • the FPGA (CLK_PHY_FPGA, pin AB13).

The FPGA can generate the PHY clock from

  • a 106.25 MHz quartz (CLK_106_25M, pin Y13)
  • the PHY quartz oscillator (CLK_PHY_25M, pin AA12)
  • one of the PHY Rx or Tx clocks (ETHA_RX_CLK, ETHA_TX_CLK, ETHB_RX_CLK, …)

The last possibility is foreseen to synchronise the clocks of slave Ethernet ports to the one of a master port.

Management Data Input Output (MDIO)

The serial Management Data Input Output (MDIO) interface is connected independently from each PHY to the FPGA.

Serial ports

The FPGA has 3 serial port connections:

  • one via an FT232RL RS232 to USB interface (USB_TXD, USB_RXD and 6 more lines)
  • 2 via a level translator
    • the first goes to a flat cable connector (UART_TXD0, UART_RXD0)
    • the second to the JTAG mini connector (UART_TXD1, UART_RXD01)

USB serial interface

The USB serial interface powers the board if jumper JP1 is set on the USB_5V side.

It provides a serial port and a JTAG interface. The serial port is connected directly to the FPGA. The JTAG interface can be connected to the FPGA programming lines via zero-Ohm resistors. This programming mode has not been tested yet.

JTAG connector

The HEI 10-pin JTAG connector provides:

  • a 3.3 V power supply
  • 4 JTAG signals for FPGA and Flash programmation
  • a minimal serial port (Rx and Tx)
  • 2 FPGA I/O lines
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