This board is a variant of the FPGA rack board, but with 4 Ethernet connectors.
|V1.0||FPGA-Rack-Ethernet4 v1.0 Schematic PDF||FPGA-Rack v1.0 UCF Files||There are different FPGA mounted: Spartan 6 XC6SLX45, Spartan 6 XC6SLX100, Spartan 6 XC6SLX150|
All 4 PHYs receive the same 25 MHz clock. This clock signal can be sourced from:
- the quartz oscillator closest to the PHYs (
- the FPGA (
CLK_PHY_FPGA, pin AB13).
The FPGA can generate the PHY clock from
- a 106.25 MHz quartz (
CLK_106_25M, pin Y13)
- the PHY quartz oscillator (
CLK_PHY_25M, pin AA12)
- one of the PHY Rx or Tx clocks (
The last possibility is foreseen to synchronise the clocks of slave Ethernet ports to the one of a master port.
Management Data Input Output (MDIO)
The serial Management Data Input Output (MDIO) interface is connected independently from each PHY to the FPGA.