Hardware/FPGARackEdison

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(VME connection)
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Connected signals are:
 
Connected signals are:
 +
* backplane controls: MCLK, RST, WCLK0, WCLK1
 
* parallel bus: A7 ÷ A0, D15 ÷ D0, en, wr, ready, freeze, mode
 
* parallel bus: A7 ÷ A0, D15 ÷ D0, en, wr, ready, freeze, mode
* SPI bus
+
* SPI bus: CLK, MISO, MOSI, CS0, CS1
 +
* I2C bus: SCl, SDa
 +
* UART: RxD, TxD
  
 
= Programmation =
 
= Programmation =

Revision as of 16:25, 26 November 2015

Contents

Board Overview

FPGA Rack Edison V1.0 3D view FPGA Rack Edison V1.0 PCB layout FPGA Rack Edison V1.0 photo

Type FPGA Rack Schematic User constraints file Description
V1.0 FPGA Rack Edison v1.0 FPGA-Rack Edison v1.0 Schematic PDF TBD 5 Intel Edison Compute Modules and Microsemi AGL1000 FPGA

The board comprises a controller FPGA and Linux microprocessor systems. It is tailored for low-power, real-time image processing. The board is compatible with the FPGA Rack Backplane for interconnecting different boards.

Hardware features

Intel Edison compute modules

The board can host up to 5 Intel Edison compute modules.

On-board communication

The FPGA connects to each compute module individually with:

  • a serial port
  • a SPI link
  • an USB FIFO circuit

Additionally, the FPGA connects to a general purpose 24-pin connector and to a VME backplane connector. The 24-pin connector is foreseen for interfacing a camera.

VME connection

The VME connector at the back is compatible with the HEI Backplane Bus, making it compatible with the other HEI VME rack components. The Edison cluster board can thus be used for controlling an instrument built out of these devices.

Connected signals are:

  • backplane controls: MCLK, RST, WCLK0, WCLK1
  • parallel bus: A7 ÷ A0, D15 ÷ D0, en, wr, ready, freeze, mode
  • SPI bus: CLK, MISO, MOSI, CS0, CS1
  • I2C bus: SCl, SDa
  • UART: RxD, TxD

Programmation

TBD

Datasheets

Internal links

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