Hardware/FPGARackHiRADDAV1
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= Core features = | = Core features = | ||
== Main board == | == Main board == | ||
| − | * | + | * 2x A/D 24bits 4MSPS (Ti ADS1675) with 2 analog paths : |
| − | ** Direct (differential | + | ** Direct (differential) |
| − | ** Through | + | ** Through operational amplifier (single/differential) |
| − | * | + | * 1x D/A 16bits 500MSPS (Maxim MAX5888), current source, with 1 analog path : |
| − | ** Direct (differential | + | ** Direct (differential) |
| − | + | ||
| − | + | ||
* 1x Xilinx Kintex7 XC7K160T-xFFG676 (XC7K70T/XC7K325T compatible) | * 1x Xilinx Kintex7 XC7K160T-xFFG676 (XC7K70T/XC7K325T compatible) | ||
** 162.24k logic cells, 25.35k slices (max 2.188Mb of distributed RAM) | ** 162.24k logic cells, 25.35k slices (max 2.188Mb of distributed RAM) | ||
** 11.7Mb block RAM (650x18Kb / 325x36Kb) | ** 11.7Mb block RAM (650x18Kb / 325x36Kb) | ||
** 600 DSP Slices | ** 600 DSP Slices | ||
| − | ** GTX | + | ** GTX I/Os |
| − | * 1x 100MHz quartz for | + | * 1x Low-jitter clock generator/distributor (AD9517-4 with 1.6GHz VCO) |
| − | * | + | * 1x 100MHz quartz for boot clock |
| − | * | + | * 1x expansion connectors with the following FPGA banks : |
| + | ** Full bank 13 (with 24 diffs or 48 single-ended + 2 single-ended, total 50 pins / Voltage range : 1.14V to 3.465V). | ||
| + | ** Full bank 32 (with 24 diffs or 48 single-ended + 2 single-ended, total 50 pins / Voltage range : 1.14V to 1.89V). | ||
| + | ** Partial bank 12 (TBD, fixed voltage : 3.0/3.3V) | ||
| + | ** Full GTX banks 115 & 116 (8x TX ,8x RX, 4x reference clocks). | ||
| + | * 1x DDR3 (32M x 8banks x 8bit width, total: 256MiB MiB) | ||
* 2x 32MiB Serial QuadSPI NOR Flash (one reserved for FPGA programming) | * 2x 32MiB Serial QuadSPI NOR Flash (one reserved for FPGA programming) | ||
| − | * | + | * 4x user RGB LEDs |
| − | * | + | * 10x user DIL switches |
| − | * 1x JTAG | + | * 1x JTAG connector |
| − | * 1x DIN41612 VME Compatible Connector 3x32 pins ( | + | * 1x DIN41612 VME Compatible Connector 3x32 pins (full HVME32) with CMOS AC termination on all signal pins (default: unsoldered) |
| − | + | ||
| − | + | ||
== Mezzanine board == | == Mezzanine board == | ||
Revision as of 17:32, 13 November 2015
|
XXThe main purpose behind this board is to have a powerful development FPGA board specialized in high-resolution data acquisition and processing.
| Type | FPGA Rack | Documentation | Description |
|---|---|---|---|
| V1.0 |  Full documentation |
Kintex7 XC7K160T-2FFG676 |
The HiRADDA set is composed of two boards : HiRADDA Core and HiRADDA Mezzanine.
HiSADDA is compatible with the FPGA Rack Backplane for interconnecting different boards with the help of the HVME16 version of the HES-SO Backplane Bus and the HES-SO VME IP Core.
Core features
Main board
- 2x A/D 24bits 4MSPS (Ti ADS1675) with 2 analog paths :
- Direct (differential)
- Through operational amplifier (single/differential)
- 1x D/A 16bits 500MSPS (Maxim MAX5888), current source, with 1 analog path :
- Direct (differential)
- 1x Xilinx Kintex7 XC7K160T-xFFG676 (XC7K70T/XC7K325T compatible)
- 162.24k logic cells, 25.35k slices (max 2.188Mb of distributed RAM)
- 11.7Mb block RAM (650x18Kb / 325x36Kb)
- 600 DSP Slices
- GTX I/Os
- 1x Low-jitter clock generator/distributor (AD9517-4 with 1.6GHz VCO)
- 1x 100MHz quartz for boot clock
- 1x expansion connectors with the following FPGA banks :
- Full bank 13 (with 24 diffs or 48 single-ended + 2 single-ended, total 50 pins / Voltage range : 1.14V to 3.465V).
- Full bank 32 (with 24 diffs or 48 single-ended + 2 single-ended, total 50 pins / Voltage range : 1.14V to 1.89V).
- Partial bank 12 (TBD, fixed voltage : 3.0/3.3V)
- Full GTX banks 115 & 116 (8x TX ,8x RX, 4x reference clocks).
- 1x DDR3 (32M x 8banks x 8bit width, total: 256MiB MiB)
- 2x 32MiB Serial QuadSPI NOR Flash (one reserved for FPGA programming)
- 4x user RGB LEDs
- 10x user DIL switches
- 1x JTAG connector
- 1x DIN41612 VME Compatible Connector 3x32 pins (full HVME32) with CMOS AC termination on all signal pins (default: unsoldered)
Mezzanine board
- 1x USB2 (micro USB connector, FTDI FT232HL)
- 1x power supply
Power supply considerations
The following power rails are produced on board :
- +A5.0V (ADS1675)
- +D1.0V (FPGA Core)
- +D1.8V (SSRAM I/Os + FPGA BANK)
- +D2.5V (SSRAM + FPGA BANK)
- +D3.0V (ADS1675 + FPGA BANK)
- +D3.3V (VME + FPGA BANK)
VME connector logic levels
The I/O bank which interfaces the VME connector is only 3.3V. Be careful with other FPGA Rack boards with 2.5V/3.3V jumper.
Programmation
This board can be programmed in 2 ways,
- First the FPGA can be directly programmed.
- Second the FPGA can be programmed via the onboard Flash memory (SPI x1/x4).
More explanation for FLASH programmation are available here.
Known issues
- None.
