Hardware/FPGARackHiRADDAV1

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XXThe main purpose behind this board is to have a powerful development FPGA board specialized in high-resolution data acquisition and processing.
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The main purpose behind this board is to have a powerful development FPGA board specialized in high-resolution data acquisition and processing.
  
 
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The HiRADDA set is composed of two boards : HiRADDA Core and HiRADDA Mezzanine.
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The HiRADDA set is composed of two or more boards :
 +
** HiRADDA Core
 +
** HiRADDA Power
 +
** n x user extension boards
  
HiSADDA is compatible with the [[Hardware/FPGARackBackplane|FPGA Rack Backplane]] for interconnecting different boards with the help of the HVME16 version of the [[Standards/HEVs_'VME'_Backplane_Bus|HES-SO Backplane Bus]] and the [[Components/IP/VME|HES-SO VME IP Core]].
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HiRADDA is compatible with the [[Hardware/FPGARackBackplane|FPGA Rack Backplane]] for interconnecting different boards with the help of the HVME16/32 version of the [[Standards/HEVs_'VME'_Backplane_Bus|HES-SO Backplane Bus]] and the [[Components/IP/VME|HES-SO VME IP Core]].
  
 
= Core features =
 
= Core features =
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** Full bank 13 (with 24 diffs or 48 single-ended + 2 single-ended, total 50 pins / Voltage range : 1.14V to 3.465V).
 
** Full bank 13 (with 24 diffs or 48 single-ended + 2 single-ended, total 50 pins / Voltage range : 1.14V to 3.465V).
 
** Full bank 32 (with 24 diffs or 48 single-ended + 2 single-ended, total 50 pins / Voltage range : 1.14V to 1.89V).
 
** Full bank 32 (with 24 diffs or 48 single-ended + 2 single-ended, total 50 pins / Voltage range : 1.14V to 1.89V).
** Partial bank 12 (TBD, fixed voltage : 3.0/3.3V)
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** Partial bank 12 (TBD, fixed voltage : +3.0/+3.3V)
** Full GTX banks 115 & 116 (8x TX ,8x RX, 4x reference clocks).
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** Full GTX banks 115 & 116 (8x TX ,8x RX, 4x reference clocks) - for PCI-Express 8x, SATA, SFP etc... use.
 +
* 1x additional connector with 8 I/Os (+3.3V).
 +
* 1x fully isolated USB2.0<->UART interface with hardware flow control.
 +
* 1x additional connector with isolated 2x input and 2x output (reduce some UART functionnalities if used).
 
* 1x DDR3 (32M x 8banks x 8bit width, total: 256MiB)
 
* 1x DDR3 (32M x 8banks x 8bit width, total: 256MiB)
 
* 2x 32MiB Serial QuadSPI NOR Flash (one reserved for FPGA programming)
 
* 2x 32MiB Serial QuadSPI NOR Flash (one reserved for FPGA programming)
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* 10x user DIL switches
 
* 10x user DIL switches
 
* 1x JTAG connector
 
* 1x JTAG connector
* 1x DIN41612 VME Compatible Connector 3x32 pins (full HVME32) with CMOS AC termination on all signal pins (default: unsoldered)
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* 1x DIN41612 VME compatible connector 3x32 pins (full HVME32, 1.8V/2.5V/3.3V) with CMOS AC termination on all signal pins (default: unsoldered)
  
 
== Mezzanine board ==
 
== Mezzanine board ==
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= Power supply considerations =
 
= Power supply considerations =
 
The following power rails are produced on board :
 
The following power rails are produced on board :
 +
* -A5.0V - Optionnal, for AOP input range extension
 
* +A5.0V (ADS1675)
 
* +A5.0V (ADS1675)
 
* +D1.0V (FPGA Core)
 
* +D1.0V (FPGA Core)
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= VME connector logic levels =
 
= VME connector logic levels =
The I/O bank which interfaces the VME connector is only 3.3V. Be careful with other FPGA Rack boards with 2.5V/3.3V jumper.
+
The I/O bank which interfaces the VME connector can be 1.8V, 2.5V or 3.3V depending on the jumper XXX position. Be careful with other FPGA Rack boards different voltage configuration.
 
   
 
   
 
= Programmation =
 
= Programmation =
This board can be programmed in 2 ways,
+
The FPGA on this board can be programmed in 2 ways :
* First the FPGA can be directly programmed.
+
* directly through JTAG interface.
* Second the FPGA can be programmed via the onboard Flash memory (SPI x1/x4).
+
* automatically on boot via the onboard FLASH memory (SPI x1/x4).
  
 
More explanation for FLASH programmation are available [[media:HISADDA_FLASHPROG.pdf‎|here]].
 
More explanation for FLASH programmation are available [[media:HISADDA_FLASHPROG.pdf‎|here]].
  
 
= Known issues =
 
= Known issues =
* None.
+
* None yet.
  
 
[[Category:Hardware]] [[Category:FPGARack]]
 
[[Category:Hardware]] [[Category:FPGARack]]

Revision as of 16:47, 13 November 2015

Contents

The main purpose behind this board is to have a powerful development FPGA board specialized in high-resolution data acquisition and processing.

Type FPGA Rack Documentation Description
V1.0
Restricted access
Full documentation
Kintex7 XC7K160T-2FFG676

The HiRADDA set is composed of two or more boards :

    • HiRADDA Core
    • HiRADDA Power
    • n x user extension boards

HiRADDA is compatible with the FPGA Rack Backplane for interconnecting different boards with the help of the HVME16/32 version of the HES-SO Backplane Bus and the HES-SO VME IP Core.

Core features

Main board

  • 2x A/D 24bits 4MSPS (Ti ADS1675) with 2 analog paths :
    • Direct (differential)
    • Through operational amplifier (single/differential)
  • 1x D/A 16bits 500MSPS (Maxim MAX5888), current source, with 1 analog path :
    • Direct (differential)
  • 1x Xilinx Kintex7 XC7K160T-xFFG676 (XC7K70T/XC7K325T compatible)
    • 162.24k logic cells, 25.35k slices (max 2.188Mb of distributed RAM)
    • 11.7Mb block RAM (650x18Kb / 325x36Kb)
    • 600 DSP Slices
    • GTX I/Os
  • 1x Low-jitter clock generator/distributor (AD9517-4 with 1.6GHz VCO)
  • 1x 100MHz quartz for boot clock
  • 1x expansion connectors with the following FPGA banks :
    • Full bank 13 (with 24 diffs or 48 single-ended + 2 single-ended, total 50 pins / Voltage range : 1.14V to 3.465V).
    • Full bank 32 (with 24 diffs or 48 single-ended + 2 single-ended, total 50 pins / Voltage range : 1.14V to 1.89V).
    • Partial bank 12 (TBD, fixed voltage : +3.0/+3.3V)
    • Full GTX banks 115 & 116 (8x TX ,8x RX, 4x reference clocks) - for PCI-Express 8x, SATA, SFP etc... use.
  • 1x additional connector with 8 I/Os (+3.3V).
  • 1x fully isolated USB2.0<->UART interface with hardware flow control.
  • 1x additional connector with isolated 2x input and 2x output (reduce some UART functionnalities if used).
  • 1x DDR3 (32M x 8banks x 8bit width, total: 256MiB)
  • 2x 32MiB Serial QuadSPI NOR Flash (one reserved for FPGA programming)
  • 4x user RGB LEDs
  • 10x user DIL switches
  • 1x JTAG connector
  • 1x DIN41612 VME compatible connector 3x32 pins (full HVME32, 1.8V/2.5V/3.3V) with CMOS AC termination on all signal pins (default: unsoldered)

Mezzanine board

  • 1x USB2 (micro USB connector, FTDI FT232HL)
  • 1x power supply

Power supply considerations

The following power rails are produced on board :

  • -A5.0V - Optionnal, for AOP input range extension
  • +A5.0V (ADS1675)
  • +D1.0V (FPGA Core)
  • +D1.8V (SSRAM I/Os + FPGA BANK)
  • +D2.5V (SSRAM + FPGA BANK)
  • +D3.0V (ADS1675 + FPGA BANK)
  • +D3.3V (VME + FPGA BANK)

VME connector logic levels

The I/O bank which interfaces the VME connector can be 1.8V, 2.5V or 3.3V depending on the jumper XXX position. Be careful with other FPGA Rack boards different voltage configuration.

Programmation

The FPGA on this board can be programmed in 2 ways :

  • directly through JTAG interface.
  • automatically on boot via the onboard FLASH memory (SPI x1/x4).

More explanation for FLASH programmation are available here.

Known issues

  • None yet.
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