Hardware/Mezzanine/Poetic

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(10 ADCs, 8 DACs)
 
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== 10 ADCs, 8 DACs ==
 
== 10 ADCs, 8 DACs ==
  
This mezzanine was developped for the FPGA Poetic Board during [https://gitlab.hevs.ch/theses/bachelor/jean-nanchen/fpga-developing-board-demonstrator Jean Nanchen's TB] (2021) and used in the NGRW project.
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This mezzanine was developped for the FPGA Poetic Board during [https://gitlab.hevs.ch/theses/bachelor/jean-nanchen/fpga-developing-board-demonstrator Jean Nanchen's TB] (2021) and used in the NGRW project with the [[Hardware/FPGAPoetic|FPGA Poetic Board]].
 
The mezzanine board has 8 SMA connectors (DAC output), 2 connectors 2x10 pins (ADC input), 1 connector 2x5 pins (SPI LVDS) and 1 connector 2x9 pins (SPARE I/O).
 
The mezzanine board has 8 SMA connectors (DAC output), 2 connectors 2x10 pins (ADC input), 1 connector 2x5 pins (SPI LVDS) and 1 connector 2x9 pins (SPARE I/O).
  

Latest revision as of 13:00, 1 October 2021

Contents

10 ADCs, 8 DACs

This mezzanine was developped for the FPGA Poetic Board during Jean Nanchen's TB (2021) and used in the NGRW project with the FPGA Poetic Board. The mezzanine board has 8 SMA connectors (DAC output), 2 connectors 2x10 pins (ADC input), 1 connector 2x5 pins (SPI LVDS) and 1 connector 2x9 pins (SPARE I/O).

This board is used for the EMVS students project day.

Version Photo Schematic
V1.0 ADC-DAC Mezzanine FPGA ADC DAC Mezza Schematic PDF

ADCs

The ADS7886 is a 6 12-Bit, 1-MSPS ADC.


DACs

The DAC084S085 is a Quad 8-Bit DAC with a serial interface that is compatible with standard SPI, QSPI, MICROWIRE, and DSP interfaces.

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