Hardware/Parallelport/heb inverter

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(Inverter board)
(Dead time)
 
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| V1.0 ||[[File:Heb inverter.jpg|200px|HEB-Synchro]] || [[Media:FPGA PP inverter.pdf|HEB-inverter Schematic PDF]] || [[Hardware/Stock_PP#HEB_Synchro|16fully mounted]]
 
| V1.0 ||[[File:Heb inverter.jpg|200px|HEB-Synchro]] || [[Media:FPGA PP inverter.pdf|HEB-inverter Schematic PDF]] || [[Hardware/Stock_PP#HEB_Synchro|16fully mounted]]
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|}
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= Dead time =
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The dead time estimation for the H-Brige has been setimated by augmenting it an monitoring the power consumption of the system.
 +
The daead time was given by a counter clocked at 66 MHZ, but with a different number of bits for each measure.
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{|class=wikitable
 +
|-
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! bit nb || dead time [ns] || current [mA]
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|-
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| 3 || 121 || 860
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|-
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| 4 || 242 || 170
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|-
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| 5 || 485 || 75
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|-
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| 5 || 970 || 70
 
|}
 
|}
  
 
[[Category:Hardware]] [[Category:Parallelport]] [[Category:HEB]]
 
[[Category:Hardware]] [[Category:Parallelport]] [[Category:HEB]]

Latest revision as of 14:59, 17 January 2022

Contents

Inverter board

The board was designed for the ETE ELN-inverter lab.

It receives 4 PWM signals to drive an H-Bridge. The bridge is followed by an LC-lowpass and a transformer.

A sigma-delta ADC reads the LC filter output and enables to adjust the output voltage.

Version Photo Schematics Stock
V1.0 HEB-Synchro HEB-inverter Schematic PDF 16fully mounted

Dead time

The dead time estimation for the H-Brige has been setimated by augmenting it an monitoring the power consumption of the system. The daead time was given by a counter clocked at 66 MHZ, but with a different number of bits for each measure.

bit nb dead time [ns] current [mA]
3 121 860
4 242 170
5 485 75
5 970 70
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