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== Math == | == Math == | ||
| + | To write a math formula in TeX, click on the math button at the top of the article edition | ||
| + | <math> | ||
| + | \operatorname{erfc}(x) = | ||
| + | \frac{2}{\sqrt{\pi}} \int_x^{\infty} e^{-t^2}\,dt = | ||
| + | \frac{e^{-x^2}}{x\sqrt{\pi}}\sum_{n=0}^\infty (-1)^n \frac{(2n)!}{n!(2x)^{2n}} | ||
| + | </math> | ||
== Article Comment == | == Article Comment == | ||
| − | + | To allow comments in a page, at the end of the article,click on the comment button at the top of the article edition | |
== Syntax Highlighting Geshi == | == Syntax Highlighting Geshi == | ||
| − | + | To highlight a code in any language, click on the SyntaxHighlighting button at the top of the article, write your code beetween the </source> tags. To select a language, you must to enter your language in the parameter lang of the tag. | |
| + | <source lang="VHDL"> | ||
| + | -- (this is a VHDL comment) | ||
| + | |||
| + | -- import std_logic from the IEEE library | ||
| + | library IEEE; | ||
| + | use IEEE.std_logic_1164.all; | ||
| + | |||
| + | -- this is the entity | ||
| + | entity ANDGATE is | ||
| + | port ( | ||
| + | I1 : in std_logic; | ||
| + | I2 : in std_logic; | ||
| + | O : out std_logic); | ||
| + | end entity ANDGATE; | ||
| + | |||
| + | architecture RTL of ANDGATE is | ||
| + | begin | ||
| + | O <= I1 and I2; | ||
| + | end architecture RTL; | ||
| + | </source> | ||
== Rss Feed == | == Rss Feed == | ||
== File & Picture, Upload & Download == | == File & Picture, Upload & Download == | ||
Revision as of 15:37, 6 February 2012
Contents |
Math
To write a math formula in TeX, click on the math button at the top of the article edition
Article Comment
To allow comments in a page, at the end of the article,click on the comment button at the top of the article edition
Syntax Highlighting Geshi
To highlight a code in any language, click on the SyntaxHighlighting button at the top of the article, write your code beetween the </source> tags. To select a language, you must to enter your language in the parameter lang of the tag.
-- (this is a VHDL comment) -- import std_logic from the IEEE library library IEEE; use IEEE.std_logic_1164.all; -- this is the entity entity ANDGATE is port ( I1 : in std_logic; I2 : in std_logic; O : out std_logic); end entity ANDGATE; architecture RTL of ANDGATE is begin O <= I1 and I2; end architecture RTL;
