# Languages/SystemVerilog/Syntax

## Integer data types

 Type States Language Size [bits] shortint 2 SystemVerilog 16 signed integer int 2 SystemVerilog 32 signed integer longint 2 SystemVerilog 64 signed integer byte 2 SystemVerilog 8 signed integer or ASCII character bit 2 SystemVerilog user-defined (default 1 bit) logic 4 SystemVerilog user-defined (default 1 bit) reg 4 Verilog-2001 user-defined (default 1 bit) integer 4 Verilog-2001 32 signed integer time 4 Verilog-2001 64 unsigned integer

The 4-state data types can have unknown (X) and high-impedance (Z) values. When a 4-state value is cast to a 2-state value, X and Z are converted to 0. When X and Z are not needed, use the 2-state types (int, bit), which execute faster.

## Arrays

### packed array

The dimensions declared before the object name (vector width) are called packed array. In memory they are represented as one contiguous set of bits.

```bit [7:0] c1;
c1 = 8'hAA;```

### unpacked array

The dimensions declared after the object name (array size) are called unpacked array.

```real u [7:0];
u = {1,2,3,4,5,6,7};```

### mixed

Mixed versions are also used (array of registers).

`reg [7:0] r1 [1:256];  // [7:0] packed, [1:256] unpacked`

## Operators

### Equality

Operands are compared bit by bit, with zero filling if the two operands do not have the same length. The result is 0 (false) or 1 (true). There are two types of Equality operators.

#### Logical Equality

The result is x, if either operand contains an x or a z.

 Operator Description a == b a equal to b, result may be unknown a != b a not equal to b, result may be unknown

#### Case Equality

Bits with x and z are included in the comparison and must match for the result to be true.

 Operator Description a === b a equal to b, including x and z a !== b a not equal to b, including x and z

### Logical

 Operator Description ! logic negation && logical and ll logical or

### Bit-wise

 Operator Description ~ negation & and l inclusive or ^ exclusive or ^~ or ~^ exclusive nor (equivalence)

## Escape sequences for format specifications

 %h, %H, %x, %X FORMAT hexadezimal %d, %D FORMAT decimal %o, %D FORMAT octal %b, %B FORMAT binary %c, %C FORMAT ASCI character %l, %L library binding information %v, %V net signal strength %m, %M hierarchical name %p, %P assignment pattern %s, %S FORMAT string %t, %T FORMAT current time %u, %U FORMAT unformatted 2-state value %z, %Z FORMAT unformatted 4-state value

 Task Function can consume simulation time(posedge, negedge, # delay) should be executed in "zero" time delay many inputs and outputs many inputs, one output return no value return a value (with return or by assigning a value to the name of the function, whereas the return function has priority) used for modeling combinational and/or sequential logic used for modeling combinational logic can call other tasks or functions can call other functions

## FORK...JOIN

 Option Description join The parent process blocks until all the processes spawned by this fork complete. join_any The parent process blocks until any one of the processes spawned by this fork complete. join_none The parent process continues to execute concurrently with all the processes spawned by the fork. The spawned processes do not start executing until the parent thread executes a blocking statement.

## OOP

This chapter serves as a short reminder of OOP concepts used in SV. For a complete overview it is advised to read Section 10 and 11 of the SV 3.1 LRM.

### Local

A variable or a function/task in a class defined as local, called private in C++, is available only to methods inside the class and not visible outside this class, not even within child classes.

### Protected

Same as local but visible to child classes. Can therefore be inherited.

### Static

#### variable

A static variable exists only once. All instances of this class share the same variable. Furthermore memory is allocated once on instantiation and never deallocated, contrary to automatic variables, who are allocated on entry of a task/function/block and deallocated on exit.

Static class properties can even be used without an object of this type.

Static functions/tasks can be called outside the class without class instantiation.

### Polymorphism

#### virtual

An object of a class can be cast as one of the parent class. If now a function/task of the object is called, it is unclear if the function of the parent class or the function of the child class should be executed. When the function is declared as virtual, always the function/task of the child class is executed. This is useful in the following example: when a function/task on a list of objects of different child classes or the parent class is executed, always the function of the corresponding class is executed. An other way to explain virtuality, is to state that a virtual method overwrites all parent methods, whereas an ordinary method only overrides the method in the current class and in it's children.

A class containing one or more virtual functions/methods has to be declared virtual too.

##### pure

A pure virtual function/task is required to be implemented by a derived class, they typically have only a declaration and no implementation. A class containing one or more pure virtual functions/methods is called abstract.

Please refer also to the corresponding article on wikipedia.

## Modularity

### Interface

Groups related wires, along with their directions (via [wiki:OpenVerificationMethodology#Modport modports]) and synchronization details (via [wiki:OpenVerificationMethodology#ClockingBlock clocking block]). The major usage of interface is to simplify the connection between modules.

#### Modport

Modports are used for specifing the direction of the signals with respect to various modules the interface connects to. Directions of signals are specified as seen from the module.

```interface my_intf;
wire x, y, z;
modport master (inout a, input x, y, output z);
modport slave  (inout a, output x, y, input z);
endinterface```

#### Clocking Block

identifies clock signals, and captures the timing and synchronization requirements of the blocks being modeled. A clocking block assembles signals that are synchronous to a particular clock, and makes their timing explicit.

If an input skew is specified then the signal is sampled at skew time units before the clock event. If output skew is specified, then output (or inout) signals are driven skew time units after the corresponding clock event.

|| #d || The skew is d time units. The time unit depends on the timescale of the block. || || #dns || The skew is d nano seconds. || || #1step || Sampling is done just before the clock. ||

```  clocking cb @(posedge clk);
default input   #1step;
default output  #1;
input  x,y;
output z;
endclocking : cb

modport master(clocking cb);```