Languages/VHDL/Examples/SynchronousBusXilinx

Synchronous pass through for Xilinx FPGA

Here is an example of a synchronous pass through for a fast bus, implement in a Xilinx Spartan6 using Xilinx tools. This example is inspired by a real industrial design [fixme:reference+link], where we have a 20 bit synchronous bus flowing through an (well filled) FPGA at 150 MHz.

[fixme : synchronous pass through drawing + vhdl entity]

Synchronous input

[fixme: drawing (rising edge, data, ...]

Principles

• You MUST use a GCLK pin for clock input, on the same bank as the input data.
• If possible, try to put all your bus and clock input on the same half-bank <ref name="ug625">Template:Cite web</ref>.
• Use the D flip-flop integrated into the input PAD
  • This can be achieved by using the "iob" attribute in the VHDL code or by placer options.
• There is a dedicated clock routing structure named BUFIO2 for sampling input pins.

What if the timing is not met ?

[fixme : explain how to find which flip-flops should be placed manually]

Inside the FPGA

• Use pipelining
  • Synthesis of fast signals through a FPGA can be difficult (the more the FPGA is full, the more it is difficult), and we're not interested in the delay introduced by our pass through.
• The synthesizer should not try to replace our pipeline by a shift-register.

 * This can be forced by the VHDL shreg_extract attribute.

• If the timing between the internal stages and the output is not met, you can try to add stages to the pipelines.
• Use the DIVCLK clock provided by the BUFIO.

Synchronous output

Principles

• Use a ODDR2 for clock output
  • The ODDR2 uses a clock and it's counter clock, so if the clock is really fast or has not a 50% duty cycle, use a PLL (DCM) for generating clock and not_clock.
• Use the D flip-flop integrated into the output PAD

Timing constraints - UCF

Here is the joke, if the data output flip-flops are placed into the PADs and the clock comes from a global clock buffer, there is nothing more to do. Here is the timing constraint that we can use for verifying the skew in the "Timing report"

Possible problems

Over-constrained design

• possible causes
  • Your input signals are split in two half bank and can't be sampled using the same IOBUF2

References

Template:Reflist template or <references />