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== News ==
 
== News ==
{{NewsBox|''Model-/QuestaSim 10.1d'' has been released with|
+
{{NewsBox|''Model-/QuestaSim 10.1d'' has been released|
 
* Continued support for VHDL 2008 and SystemVerilog.
 
* Continued support for VHDL 2008 and SystemVerilog.
 
* Minor GUI improvements and bugfixes
 
* Minor GUI improvements and bugfixes
 
* the new ''Register Assistant UVM (RUVM)'' in Questa
 
* the new ''Register Assistant UVM (RUVM)'' in Questa
 
Register Assistant UVM consists of a single, scalable and extensible data model that enables proficient management of the register information and changes and automatically generates or updates the UVM Register package for use within Questa Sim. RUVM can import register and memory specifications from spreadsheets (CSV) describing the hierarchy of blocks, sub-blocks, maps, registers, fields and memories, while DRC checks ensure consistency. RUVM is part of a complete register management solution available in HDL Designer which can import register and memory specifications from a variety of sources including IP-XACT, XML and spreadsheet (CSV) and automatically generate consistent UVM and OVM register packages for verification, synthesizable RTL code for the hardware design, C Header definitions for the software/firmware development, and HTML hyperlinked documentation for communication.}}
 
Register Assistant UVM consists of a single, scalable and extensible data model that enables proficient management of the register information and changes and automatically generates or updates the UVM Register package for use within Questa Sim. RUVM can import register and memory specifications from spreadsheets (CSV) describing the hierarchy of blocks, sub-blocks, maps, registers, fields and memories, while DRC checks ensure consistency. RUVM is part of a complete register management solution available in HDL Designer which can import register and memory specifications from a variety of sources including IP-XACT, XML and spreadsheet (CSV) and automatically generate consistent UVM and OVM register packages for verification, synthesizable RTL code for the hardware design, C Header definitions for the software/firmware development, and HTML hyperlinked documentation for communication.}}
{{NewsBox|[http://www.microsemi.com/ Microsemi] [http://investor.microsemi.com/releasedetail.cfm?ReleaseID711708 revealed] the new ''[http://www.actel.com/fpga/SmartFusion2/ SmartFusion®2]'' SoC with|
+
{{NewsBox|[http://www.microsemi.com/ Microsemi] [http://investor.microsemi.com/releasedetail.cfm?ReleaseID711708 revealed] the new ''[http://www.actel.com/fpga/SmartFusion2/ SmartFusion®2]'' SoC|
 
* 5K - 120K LUTs,  190k - 4.5Mbit RAM, 11 -240 Math (DSP) blocks
 
* 5K - 120K LUTs,  190k - 4.5Mbit RAM, 11 -240 Math (DSP) blocks
 
* ''166 MHz ARM® Cortex™-M3'' microprocessor with 8Kbyte Instruction Cache
 
* ''166 MHz ARM® Cortex™-M3'' microprocessor with 8Kbyte Instruction Cache
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* but ''no more'' DAC/ADC
 
* but ''no more'' DAC/ADC
 
* samples available now, first production silicon slated for early 2013}}
 
* samples available now, first production silicon slated for early 2013}}
{{NewsBox|''[[Tools/Synopsys_Synplify|Synplify]] [[Tools/Versions#2012.09|2012.9]]'' is now available on  [[User:Guo|guo]]'s [ftp://fpga:fpga@153.109.5.248 Software Server] including|
+
{{NewsBox|''[[Tools/Synopsys_Synplify|Synplify]] [[Tools/Versions#2012.09|2012.9]]'' is now available on  [[User:Guo|guo]]'s [ftp://fpga:fpga@153.109.5.248 Software Server]|
 
* Xilinx Vivado PAR support
 
* Xilinx Vivado PAR support
 
* new Timing Report View
 
* new Timing Report View
 
* compiler enhancements (SV, VHDL2008, ...)}}
 
* compiler enhancements (SV, VHDL2008, ...)}}
{{NewsBox|[http://qt-project.org/wiki/Qt-5-Beta ''Qt 5 Beta''] has been released with focus on|
+
{{NewsBox|[http://qt-project.org/wiki/Qt-5-Beta ''Qt 5 Beta''] has been released|
 
* Faster GUI with ''QML'' and ''QtQuick'' with special focus on low cost HW environments (mobile, embedded).
 
* Faster GUI with ''QML'' and ''QtQuick'' with special focus on low cost HW environments (mobile, embedded).
 
* Built-in OpenGL (ES) support.
 
* Built-in OpenGL (ES) support.
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For the full list get the [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_2/irn.pdf Release Notes Guide].
 
For the full list get the [http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_2/irn.pdf Release Notes Guide].
 
[http://www.xilinx.com/products/design-tools/vivado/index.htm Vivado] is a new IP and system-centric IDE in the ''Design Edition'' and an added focus on HLS in the ''System Edition''.}}
 
[http://www.xilinx.com/products/design-tools/vivado/index.htm Vivado] is a new IP and system-centric IDE in the ''Design Edition'' and an added focus on HLS in the ''System Edition''.}}
{{NewsBox|''HDL-Designer 2012.1'' has been released with|
+
{{NewsBox|''HDL-Designer 2012.1'' has been released|
 
* several bugfixes
 
* several bugfixes
 
* new license format
 
* new license format

Revision as of 14:11, 13 November 2012

Contents

Welcome to the HES-SO Valais Wallis Wiki of the Infotronics Unit

HESSO Logo
This is the knowledge database of the HES-SO Valais Wallis Institute of Systems Engineering Infotronics Unit. It's the place to share experiences, findings, how-to's and everything else about HDL, Telecom, Embedded Systems and related topics.




News

  • Continued support for VHDL 2008 and SystemVerilog.
  • Minor GUI improvements and bugfixes
  • the new Register Assistant UVM (RUVM) in Questa

Register Assistant UVM consists of a single, scalable and extensible data model that enables proficient management of the register information and changes and automatically generates or updates the UVM Register package for use within Questa Sim. RUVM can import register and memory specifications from spreadsheets (CSV) describing the hierarchy of blocks, sub-blocks, maps, registers, fields and memories, while DRC checks ensure consistency. RUVM is part of a complete register management solution available in HDL Designer which can import register and memory specifications from a variety of sources including IP-XACT, XML and spreadsheet (CSV) and automatically generate consistent UVM and OVM register packages for verification, synthesizable RTL code for the hardware design, C Header definitions for the software/firmware development, and HTML hyperlinked documentation for communication.

Model-/QuestaSim 10.1d has been released

{{{3}}}

  • 5K - 120K LUTs, 190k - 4.5Mbit RAM, 11 -240 Math (DSP) blocks
  • 166 MHz ARM® Cortex™-M3 microprocessor with 8Kbyte Instruction Cache
    • connects to USB 2.0 HS OTG, CAN, SPI, I2C and Gigabit Ethernet
  • static power 10mW during operation on the 50K LUT device
  • 0 - 16 5Gbps SERDES, PCIe, XAUI / XGXS+ Native SERDES
  • Hard 800 mbps DDR2/3 controllers with SECDED (aka ECC or EDAC) protection
  • but no more DAC/ADC
  • samples available now, first production silicon slated for early 2013

Microsemi revealed the new SmartFusion®2 SoC

{{{3}}}

  • Xilinx Vivado PAR support
  • new Timing Report View
  • compiler enhancements (SV, VHDL2008, ...)

Synplify 2012.9 is now available on guo's Software Server

{{{3}}}

  • Faster GUI with QML and QtQuick with special focus on low cost HW environments (mobile, embedded).
  • Built-in OpenGL (ES) support.
  • Easy porting from Qt 4.

Qt 5 Beta has been released

{{{3}}}

For ISE there are some minor MicroBlaze updates, increased device support (especially Zynq-7000 EPP), further AXI support and other various updates. For the full list get the Release Notes Guide. Vivado is a new IP and system-centric IDE in the Design Edition and an added focus on HLS in the System Edition.

Xilinx ISE 14.2 has been released together with the first official release of the new Xilinx Vivado Design Suite 2012.2

{{{3}}}

  • several bugfixes
  • new license format

Note: Please contact Guo if you like to use this version!

HDL-Designer 2012.1 has been released

{{{3}}}

This bugfix release is available for download now.

UVM 1.1b

{{{3}}}

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