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== News == | == News == | ||
'''HDL-Designer 2011.1''' has been released with: | '''HDL-Designer 2011.1''' has been released with: | ||
− | * | + | * Improved VHDL 2008 Language Support (Unconstrained Element Types, Sensitivity list "all" construct, Matching case statements) |
− | * | + | * Support for SVN 1.7 |
'''Xilinx ISE 14.1''' has been released. Interesting features: | '''Xilinx ISE 14.1''' has been released. Interesting features: |
Revision as of 13:13, 21 May 2012
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Welcome to the HES-SO Valais Wallis EDA Wiki
This is the knowledge database of the HES-SO Valais Wallis Digital Hardware Team. It's the place to share experiences, findings, how-to's and everything else about EDA, HDL, FPGAs and related topics.
News
HDL-Designer 2011.1 has been released with:
- Improved VHDL 2008 Language Support (Unconstrained Element Types, Sensitivity list "all" construct, Matching case statements)
- Support for SVN 1.7
Xilinx ISE 14.1 has been released. Interesting features:
- Further integration of the 7 series, especially Zynq-7000 EPP
- MicroBlaze performance improvements
- extended AXI4 support
ModelSim/Questa 10.1b has been released. Interesting new features:
- Further support for VHDL 2008.
- Increased usability of SystemVerilog and UVM.
Content
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