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= News = | = News = | ||
| + | {{NewsBox|''Model-/QuestaSim 10.0f'' is now available on [[User:Guo|guo]]'s [ftp://fpga:fpga@153.109.5.248 Software Server]| | ||
| + | This update brings following new features to the ''10.0'' release: | ||
| + | * Improved GUI performance – Improved structure window and objects window | ||
| + | * VHDL Improvements - Support for significant portions of VHDL 2008 and Preservation | ||
| + | of user case in identifiers | ||
| + | * New advanced debug features including schematic view debug and automatic causality | ||
| + | tracing | ||
| + | * Improved WLF debugging and new Code Coverage Analysis Pane}} | ||
{{NewsBox|''[[Tools/Synopsys_Synplify|Synplify]] [[Tools/Versions#2013.03|2013.3]]'' is now available on [[User:Guo|guo]]'s [ftp://fpga:fpga@153.109.5.248 Software Server]| | {{NewsBox|''[[Tools/Synopsys_Synplify|Synplify]] [[Tools/Versions#2013.03|2013.3]]'' is now available on [[User:Guo|guo]]'s [ftp://fpga:fpga@153.109.5.248 Software Server]| | ||
* Improved Altera and Xilinx Vivado support | * Improved Altera and Xilinx Vivado support | ||
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* Expanded SystemVerilog Support | * Expanded SystemVerilog Support | ||
* Improved Physical Plus for Xilinx devices}} | * Improved Physical Plus for Xilinx devices}} | ||
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{{NewsBox|The ''IEEE Std 1800-2012'' a.k.a. ''SystemVerilog'' is available for [http://standards.ieee.org/getieee/1800/download/1800-2012.pdf download]| | {{NewsBox|The ''IEEE Std 1800-2012'' a.k.a. ''SystemVerilog'' is available for [http://standards.ieee.org/getieee/1800/download/1800-2012.pdf download]| | ||
The '''31 new features''', '''60 clarifications''' and '''71 corrections''' of the standard include: | The '''31 new features''', '''60 clarifications''' and '''71 corrections''' of the standard include: | ||
Revision as of 08:45, 11 April 2013
Welcome to the HES-SO Valais Wallis Wiki of the Infotronics Unit
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Use the Navigation to the left to enter the different sections or follow any of the following links:
News
This update brings following new features to the 10.0 release:
- Improved GUI performance – Improved structure window and objects window
- VHDL Improvements - Support for significant portions of VHDL 2008 and Preservation
of user case in identifiers
- New advanced debug features including schematic view debug and automatic causality
tracing
- Improved WLF debugging and new Code Coverage Analysis Pane
Model-/QuestaSim 10.0f is now available on guo's Software Server
{{{3}}}
- Improved Altera and Xilinx Vivado support
- New Microsemi SmartFusion2 Device
- Expanded SystemVerilog Support
- Improved Physical Plus for Xilinx devices
Synplify 2013.3 is now available on guo's Software Server
{{{3}}}
The 31 new features, 60 clarifications and 71 corrections of the standard include:
- Multiple inheritance !
- Soft constraints
- Uniqueness constraints
- A different global clock can be defined for each hierarchy scope
More infos here
The IEEE Std 1800-2012 a.k.a. SystemVerilog is available for download
{{{3}}}
- System Generator for DSP updates
- HLS imporvements
- further Device Support for Virtex-7, Artix-7 and Zynq-7000
Xilinx ISE 14.4 and Xilinx Vivado Design Suite 2012.4 introducing the Vivado WebPACK Tool have been released
{{{3}}}
- Faster GUI with QML and QtQuick with special focus on low cost HW environments (mobile, embedded).
- Built-in OpenGL (ES) support
- Webkit and HTML5
- Easy porting from Qt
After 7 years of development, Qt 5.0, centered around Qt Quick with the full capabilities of OpenGL/OpenGL ES, has been released.
{{{3}}}
- 5K - 120K LUTs, 190k - 4.5Mbit RAM, 11 -240 Math (DSP) blocks
- 166 MHz ARM® Cortex™-M3 microprocessor with 8Kbyte Instruction Cache
- connects to USB 2.0 HS OTG, CAN, SPI, I2C and Gigabit Ethernet
- static power 10mW during operation on the 50K LUT device
- 0 - 16 5Gbps SERDES, PCIe, XAUI / XGXS+ Native SERDES
- Hard 800 mbps DDR2/3 controllers with SECDED (aka ECC or EDAC) protection
- but no more DAC/ADC
- samples available now, first production silicon slated for early 2013
Microsemi revealed the new SmartFusion®2 SoC
{{{3}}}
- several bugfixes
- new license format
HDL-Designer 2012.1 has been released
{{{3}}}
This bugfix release is available for download now.
UVM 1.1b
{{{3}}}
