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| − | {{NewsBox|''Model-/QuestaSim 10.0f'' is now available on [[User:Guo|guo]]'s [ftp://fpga:fpga@153.109.5.248 Software Server]| | + | {{NewsBox|''[[Tools/Xilinx_ISE|Xilinx ISE]] [[Tools/Versions#14.5|14.5]]'' is now available on [[User:Guo|guo]]'s [ftp://fpga:fpga@153.109.5.248 Software Server]|24 April 2013| |
| + | * IP updates | ||
| + | * further Device Support for Virtex-7, Zynq-7000 and Defenense-Grade Kintex-7Q, Virtex-7Q}} | ||
| + | {{NewsBox|''Model-/QuestaSim 10.0f'' is now available on [[User:Guo|guo]]'s [ftp://fpga:fpga@153.109.5.248 Software Server]|| | ||
This update brings following new features to the ''10.0'' release: | This update brings following new features to the ''10.0'' release: | ||
* Improved GUI performance – Improved structure window and objects window | * Improved GUI performance – Improved structure window and objects window | ||
| Line 22: | Line 25: | ||
tracing | tracing | ||
* Improved WLF debugging and new Code Coverage Analysis Pane}} | * Improved WLF debugging and new Code Coverage Analysis Pane}} | ||
| − | {{NewsBox|''[[Tools/Synopsys_Synplify|Synplify]] [[Tools/Versions#2013.03|2013.3]]'' is now available on [[User:Guo|guo]]'s [ftp://fpga:fpga@153.109.5.248 Software Server]| | + | {{NewsBox|''[[Tools/Synopsys_Synplify|Synplify]] [[Tools/Versions#2013.03|2013.3]]'' is now available on [[User:Guo|guo]]'s [ftp://fpga:fpga@153.109.5.248 Software Server]|| |
* Improved Altera and Xilinx Vivado support | * Improved Altera and Xilinx Vivado support | ||
* New Microsemi SmartFusion2 Device | * New Microsemi SmartFusion2 Device | ||
* Expanded SystemVerilog Support | * Expanded SystemVerilog Support | ||
* Improved Physical Plus for Xilinx devices}} | * Improved Physical Plus for Xilinx devices}} | ||
| − | {{NewsBox|The ''IEEE Std 1800-2012'' a.k.a. ''SystemVerilog'' is available for [http://standards.ieee.org/getieee/1800/download/1800-2012.pdf download]| | + | {{NewsBox|The ''IEEE Std 1800-2012'' a.k.a. ''SystemVerilog'' is available for [http://standards.ieee.org/getieee/1800/download/1800-2012.pdf download]|| |
The '''31 new features''', '''60 clarifications''' and '''71 corrections''' of the standard include: | The '''31 new features''', '''60 clarifications''' and '''71 corrections''' of the standard include: | ||
* Multiple inheritance ! | * Multiple inheritance ! | ||
| Line 34: | Line 37: | ||
* A different global clock can be defined for each hierarchy scope | * A different global clock can be defined for each hierarchy scope | ||
More infos [http://www.sutherland-hdl.com/papers/2012-DVCon_SystemVerilog-2012_presentation.pdf here]}} | More infos [http://www.sutherland-hdl.com/papers/2012-DVCon_SystemVerilog-2012_presentation.pdf here]}} | ||
| − | + | {{NewsBox|UIT Wiki Presentation|| | |
| − | + | ||
| − | + | ||
| − | + | ||
| − | {{NewsBox|UIT Wiki Presentation| | + | |
The presentation slides can be downloaded [[Media:Presentation_en_UITWiki.pdf|here]].}} | The presentation slides can be downloaded [[Media:Presentation_en_UITWiki.pdf|here]].}} | ||
| − | {{NewsBox|After 7 years of development, [http://qt-project.org/qt5 ''Qt 5.0''], centered around Qt Quick with the full capabilities of OpenGL/OpenGL ES, has been released.| | + | {{NewsBox|After 7 years of development, [http://qt-project.org/qt5 ''Qt 5.0''], centered around Qt Quick with the full capabilities of OpenGL/OpenGL ES, has been released.|| |
Note: [http://qt-project.org/forums/viewthread/22883/#106962 due to problems with ''QtWebkit'' there are no official ''MinGW'' builds yet, but a patch is previewed before end of January 2013] | Note: [http://qt-project.org/forums/viewthread/22883/#106962 due to problems with ''QtWebkit'' there are no official ''MinGW'' builds yet, but a patch is previewed before end of January 2013] | ||
* Faster GUI with ''QML'' and ''QtQuick'' with special focus on low cost HW environments (mobile, embedded). | * Faster GUI with ''QML'' and ''QtQuick'' with special focus on low cost HW environments (mobile, embedded). | ||
| Line 47: | Line 46: | ||
* Easy porting from Qt | * Easy porting from Qt | ||
}} | }} | ||
| − | {{NewsBox|[http://www.microsemi.com/ Microsemi] [http://investor.microsemi.com/releasedetail.cfm?ReleaseID711708 revealed] the new ''[http://www.actel.com/fpga/SmartFusion2/ SmartFusion®2]'' SoC| | + | {{NewsBox|[http://www.microsemi.com/ Microsemi] [http://investor.microsemi.com/releasedetail.cfm?ReleaseID711708 revealed] the new ''[http://www.actel.com/fpga/SmartFusion2/ SmartFusion®2]'' SoC|| |
* 5K - 120K LUTs, 190k - 4.5Mbit RAM, 11 -240 Math (DSP) blocks | * 5K - 120K LUTs, 190k - 4.5Mbit RAM, 11 -240 Math (DSP) blocks | ||
* ''166 MHz ARM® Cortex™-M3'' microprocessor with 8Kbyte Instruction Cache | * ''166 MHz ARM® Cortex™-M3'' microprocessor with 8Kbyte Instruction Cache | ||
| Line 56: | Line 55: | ||
* but ''no more'' DAC/ADC | * but ''no more'' DAC/ADC | ||
* samples available now, first production silicon slated for early 2013}} | * samples available now, first production silicon slated for early 2013}} | ||
| − | {{NewsBox|''HDL-Designer 2012.1'' has been released| | + | {{NewsBox|''HDL-Designer 2012.1'' has been released|| |
* several bugfixes | * several bugfixes | ||
* new license format}} | * new license format}} | ||
| − | {{NewsBox|''UVM 1.1b''|This bugfix release is available for download now.}} | + | {{NewsBox|''UVM 1.1b''||This bugfix release is available for download now.}} |
Revision as of 09:06, 24 April 2013
Welcome to the HES-SO Valais Wallis Wiki of the Infotronics Unit
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News
24 April 2013
Xilinx ISE 14.5 is now available on guo's Software Server
- IP updates
- further Device Support for Virtex-7, Zynq-7000 and Defenense-Grade Kintex-7Q, Virtex-7Q
Model-/QuestaSim 10.0f is now available on guo's Software Server
This update brings following new features to the 10.0 release:
- Improved GUI performance – Improved structure window and objects window
- VHDL Improvements - Support for significant portions of VHDL 2008 and Preservation
of user case in identifiers
- New advanced debug features including schematic view debug and automatic causality
tracing
- Improved WLF debugging and new Code Coverage Analysis Pane
Synplify 2013.3 is now available on guo's Software Server
- Improved Altera and Xilinx Vivado support
- New Microsemi SmartFusion2 Device
- Expanded SystemVerilog Support
- Improved Physical Plus for Xilinx devices
The IEEE Std 1800-2012 a.k.a. SystemVerilog is available for download
The 31 new features, 60 clarifications and 71 corrections of the standard include:
- Multiple inheritance !
- Soft constraints
- Uniqueness constraints
- A different global clock can be defined for each hierarchy scope
More infos here
After 7 years of development, Qt 5.0, centered around Qt Quick with the full capabilities of OpenGL/OpenGL ES, has been released.
- Faster GUI with QML and QtQuick with special focus on low cost HW environments (mobile, embedded).
- Built-in OpenGL (ES) support
- Webkit and HTML5
- Easy porting from Qt
Microsemi revealed the new SmartFusion®2 SoC
- 5K - 120K LUTs, 190k - 4.5Mbit RAM, 11 -240 Math (DSP) blocks
- 166 MHz ARM® Cortex™-M3 microprocessor with 8Kbyte Instruction Cache
- connects to USB 2.0 HS OTG, CAN, SPI, I2C and Gigabit Ethernet
- static power 10mW during operation on the 50K LUT device
- 0 - 16 5Gbps SERDES, PCIe, XAUI / XGXS+ Native SERDES
- Hard 800 mbps DDR2/3 controllers with SECDED (aka ECC or EDAC) protection
- but no more DAC/ADC
- samples available now, first production silicon slated for early 2013
HDL-Designer 2012.1 has been released
- several bugfixes
- new license format
UVM 1.1b
This bugfix release is available for download now.
