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Revision as of 09:53, 6 June 2012


Welcome to the HES-SO Valais Wallis EDA Wiki

This is the knowledge database of the HES-SO Valais Wallis Digital Hardware Team. It's the place to share experiences, findings, how-to's and everything else about EDA, HDL, FPGAs and related topics.


Don't forget to come to the EDAwiki presentation by zas

  • 11h00
  • A310

Model-/QuestaSim 6.6g has been released with:

  • Improved mixed language (SV/VHDL) support
  • Optimizations and performance enhancements
  • Oscillation/0-delay loop identification and debug

Synplify 2012.3-SP1 has been released with:

  • ISE 14.1 Support including Xilinx 7 series
  • Safe FSM with user-defined and automated recovery logic and error correction

HDL-Designer 2011.1 has been released with:

  • Improved VHDL 2008 Language Support (Unconstrained Element Types, Sensitivity list "all" construct, Matching case statements)
  • Support for SVN 1.7

Xilinx ISE 14.1 has been released with:

  • Further integration of the 7 series, especially Zynq-7000 EPP
  • MicroBlaze performance improvements
  • extended AXI4 support

Model-/QuestaSim 10.1b has been released with:

  • Further support for VHDL 2008.
  • Increased usability of SystemVerilog and UVM.


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