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== News == | == News == | ||
| + | '''Model-/QuestaSim 10.1c''' have been released with: | ||
| + | * Further support for VHDL 2008 (enhanced generics, unconstrained arrays). | ||
| + | * Improved debugging of SystemVerilog and UVM. | ||
| + | * Minor GUI improvements. | ||
| + | ---- | ||
'''Xilinx ISE 14.2''' has been released together with the first official release of the new '''Xilinx Vivado Design Suite 2012.2'''. | '''Xilinx ISE 14.2''' has been released together with the first official release of the new '''Xilinx Vivado Design Suite 2012.2'''. | ||
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* ISE 14.1 Support including Xilinx 7 series | * ISE 14.1 Support including Xilinx 7 series | ||
* Safe FSM with user-defined and automated recovery logic and error correction | * Safe FSM with user-defined and automated recovery logic and error correction | ||
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== Content == | == Content == | ||
Revision as of 08:15, 3 August 2012
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Welcome to the HES-SO Valais Wallis Wiki of the Infotronics Unit
This is the knowledge database of the HES-SO Valais Wallis Infotronics Unit. It's the place to share experiences, findings, how-to's and everything else about EDA, Telecom, Embedded Systems and related topics.
News
Model-/QuestaSim 10.1c have been released with:
- Further support for VHDL 2008 (enhanced generics, unconstrained arrays).
- Improved debugging of SystemVerilog and UVM.
- Minor GUI improvements.
Xilinx ISE 14.2 has been released together with the first official release of the new Xilinx Vivado Design Suite 2012.2.
For ISE there are some minor MicroBlaze updates, increased device support (especially Zynq-7000 EPP), further AXI support and other various updates. For the full list get the Release Notes Guide.
Vivado is a new IP and system-centric IDE in the Design Edition and an added focus on HLS in the System Edition.
HDL-Designer 2012.1 has been released with:
- several bugfixes
- new license format
Note: Please contact Guo if you like to use this version!
The UIT wiki serves as information hub for the whole unit.
A bugfix release of UVM 1.1b is available for download now.
Model-/QuestaSim 6.6g has been released with:
- Improved mixed language (SV/VHDL) support
- Optimizations and performance enhancements
- Oscillation/0-delay loop identification and debug
Synplify 2012.3-SP1 has been released with:
- ISE 14.1 Support including Xilinx 7 series
- Safe FSM with user-defined and automated recovery logic and error correction
Content
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- Standards
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- Links
- Articles
- Help
- Sandbox for test purposes
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