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Welcome to the HES-SO Valais Wallis Wiki of the Infotronics Unit

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This is the knowledge database of the HES-SO Valais Wallis Institute of Systems Engineering Infotronics Unit. It's the place to share experiences, findings, how-to's and everything else about HDL, Telecom, Embedded Systems and related topics.


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Getting started

Use the Navigation to the left to enter the different sections or follow any of the following links:

News

This is a standard update release and includes bug fixes and enhancements.

Modle-/QuestaSim 10.2a is now available on guo's Software Server

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The 31 new features, 60 clarifications and 71 corrections of the standard include:

  • Multiple inheritance !
  • Soft constraints
  • Uniqueness constraints
  • A different global clock can be defined for each hierarchy scope

More infos here

The IEEE Std 1800-2012 a.k.a. SystemVerilog is available for download

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  • System Generator for DSP updates
  • HLS imporvements
  • further Device Support for Virtex-7, Artix-7 and Zynq-7000

Xilinx ISE 14.4 and Xilinx Vivado Design Suite 2012.4 introducing the Vivado WebPACK Tool have been released

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The presentation slides can be downloaded here.

UIT Wiki Presentation

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Note: due to problems with QtWebkit there are no official MinGW builds yet, but a patch is previewed before end of January 2013

  • Faster GUI with QML and QtQuick with special focus on low cost HW environments (mobile, embedded).
  • Built-in OpenGL (ES) support
  • Webkit and HTML5
  • Easy porting from Qt

After 7 years of development, Qt 5.0, centered around Qt Quick with the full capabilities of OpenGL/OpenGL ES, has been released.

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  • 5K - 120K LUTs, 190k - 4.5Mbit RAM, 11 -240 Math (DSP) blocks
  • 166 MHz ARM® Cortex™-M3 microprocessor with 8Kbyte Instruction Cache
    • connects to USB 2.0 HS OTG, CAN, SPI, I2C and Gigabit Ethernet
  • static power 10mW during operation on the 50K LUT device
  • 0 - 16 5Gbps SERDES, PCIe, XAUI / XGXS+ Native SERDES
  • Hard 800 mbps DDR2/3 controllers with SECDED (aka ECC or EDAC) protection
  • but no more DAC/ADC
  • samples available now, first production silicon slated for early 2013

Microsemi revealed the new SmartFusion®2 SoC

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  • Xilinx Vivado PAR support
  • new Timing Report View
  • compiler enhancements (SV, VHDL2008, ...)

Synplify 2012.9 is now available on guo's Software Server

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  • several bugfixes
  • new license format

HDL-Designer 2012.1 has been released

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This bugfix release is available for download now.

UVM 1.1b

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