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Welcome to the HES-SO Valais Wallis Wiki of the Infotronics Unit

This is the knowledge database of the HES-SO Valais Wallis Infotronics Unit. It's the place to share experiences, findings, how-to's and everything else about EDA, Telecom, Embedded Systems and related topics.

News

HDL-Designer 2012.1 has been released with:

  • several bugfixes
  • new license format

Note: Please contact Guo if you like to use this version!


The UIT wiki serves as information hub for the whole unit.


A bugfix release of UVM 1.1b is available for download now.


Model-/QuestaSim 6.6g has been released with:

  • Improved mixed language (SV/VHDL) support
  • Optimizations and performance enhancements
  • Oscillation/0-delay loop identification and debug

Synplify 2012.3-SP1 has been released with:

  • ISE 14.1 Support including Xilinx 7 series
  • Safe FSM with user-defined and automated recovery logic and error correction

Xilinx ISE 14.1 has been released with:

  • Further integration of the 7 series, especially Zynq-7000 EPP
  • MicroBlaze performance improvements
  • extended AXI4 support

Model-/QuestaSim 10.1b has been released with:

  • Further support for VHDL 2008.
  • Increased usability of SystemVerilog and UVM.

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