Welcome to the HES-SO Valais Wallis Wiki of the Infotronics Unit
This is the knowledge database of the HES-SO Valais Wallis Institute of Systems Engineering Infotronics Unit. It's the place to share experiences, findings, how-to's and everything else about HDL, Telecom, Embedded Systems and related topics.
- 5K - 120K LUTs, 190k - 4.5Mbit RAM, 11 -240 Math (DSP) blocks
- 166 MHz ARM® Cortex™-M3 microprocessor with 8Kbyte Instruction Cache
- connects to USB 2.0 HS OTG, CAN, SPI, I2C and Gigabit Ethernet
- static power 10mW during operation on the 50K LUT device
- 16x 5Gbps SERDES, PCIe, XAUI / XGXS+ Native SERDES
- Hard 800 mbps DDR2/3 controllers with SECDED (aka ECC or EDAC) protection
- samples available now, first production silicon slated for early 2013
- Xilinx Vivado PAR support
- new Timing Report View
- compiler enhancements (SV, VHDL2008, ...)
Qt 5 Beta has been released with focus on:
- Faster GUI with QML and QtQuick with special focus on low cost HW environments (mobile, embedded).
- Built-in OpenGL (ES) support.
- Easy porting from Qt 4.
Model-/QuestaSim 10.1c have been released with:
- Further support for VHDL 2008 (enhanced generics, unconstrained arrays).
- Improved debugging of SystemVerilog and UVM.
- Minor GUI improvements.
Xilinx ISE 14.2 has been released together with the first official release of the new Xilinx Vivado Design Suite 2012.2.
For ISE there are some minor MicroBlaze updates, increased device support (especially Zynq-7000 EPP), further AXI support and other various updates. For the full list get the Release Notes Guide.
Vivado is a new IP and system-centric IDE in the Design Edition and an added focus on HLS in the System Edition.
HDL-Designer 2012.1 has been released with:
- several bugfixes
- new license format
Note: Please contact Guo if you like to use this version!
A bugfix release of UVM 1.1b is available for download now.
- Sandbox for test purposes
Sign up to our RSS Feed -> UIT Wiki RSS Feed