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{{NewsBox|UIT Wiki Presentation|
{{NewsBox|UIT Wiki Presentation|
To mark the official start of the HES-SO UIT Wiki a presentation will be held on 24 January 2013 in Room BE06
To mark the official start of the HES-SO UIT Wiki a presentation will be held on 24 January 2013 in Room BE06
The Presentation Slides can be downloaded [[Media:Presentation_en_UITWiki.pdf‎‎|here]]
The presentation slides can be downloaded [[Media:Presentation_en_UITWiki.pdf‎‎|here]]

Revision as of 11:06, 7 February 2013

Welcome to the HES-SO Valais Wallis Wiki of the Infotronics Unit


HESSO Valais Wallis Logo
This is the knowledge database of the HES-SO Valais Wallis Institute of Systems Engineering Infotronics Unit. It's the place to share experiences, findings, how-to's and everything else about HDL, Telecom, Embedded Systems and related topics.

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Getting started

Use the Navigation to the left to enter the different sections or follow any of the following links:


To mark the official start of the HES-SO UIT Wiki a presentation will be held on 24 January 2013 in Room BE06 The presentation slides can be downloaded here

UIT Wiki Presentation


Note: due to problems with QtWebkit there are no official MinGW builds yet, but a patch is previewed before end of January 2013

  • Faster GUI with QML and QtQuick with special focus on low cost HW environments (mobile, embedded).
  • Built-in OpenGL (ES) support
  • Webkit and HTML5
  • Easy porting from Qt

After 7 years of development, Qt 5.0, centered around Qt Quick with the full capabilities of OpenGL/OpenGL ES, has been released.


  • Continued support for VHDL 2008 and SystemVerilog.
  • Minor GUI improvements and bugfixes
  • New Register Assistant UVM (RUVM) in Questa:

Register Assistant UVM consists of a single, scalable and extensible data model that enables proficient management of the register information and changes and automatically generates or updates the UVM Register package for use within Questa Sim. RUVM can import register and memory specifications from spreadsheets (CSV) describing the hierarchy of blocks, sub-blocks, maps, registers, fields and memories, while DRC checks ensure consistency. RUVM is part of a complete register management solution available in HDL Designer which can import register and memory specifications from a variety of sources including IP-XACT, XML and spreadsheet (CSV) and automatically generate consistent UVM and OVM register packages for verification, synthesizable RTL code for the hardware design, C Header definitions for the software/firmware development, and HTML hyperlinked documentation for communication.

Model-/QuestaSim 10.1d has been released


  • 5K - 120K LUTs, 190k - 4.5Mbit RAM, 11 -240 Math (DSP) blocks
  • 166 MHz ARM® Cortex™-M3 microprocessor with 8Kbyte Instruction Cache
    • connects to USB 2.0 HS OTG, CAN, SPI, I2C and Gigabit Ethernet
  • static power 10mW during operation on the 50K LUT device
  • 0 - 16 5Gbps SERDES, PCIe, XAUI / XGXS+ Native SERDES
  • Hard 800 mbps DDR2/3 controllers with SECDED (aka ECC or EDAC) protection
  • but no more DAC/ADC
  • samples available now, first production silicon slated for early 2013

Microsemi revealed the new SmartFusion®2 SoC


  • Xilinx Vivado PAR support
  • new Timing Report View
  • compiler enhancements (SV, VHDL2008, ...)

Synplify 2012.9 is now available on guo's Software Server


For ISE there are some minor MicroBlaze updates, increased device support (especially Zynq-7000 EPP), further AXI support and other various updates. For the full list get the Release Notes Guide. Vivado is a new IP and system-centric IDE in the Design Edition and an added focus on HLS in the System Edition.

Xilinx ISE 14.2 has been released together with the first official release of the new Xilinx Vivado Design Suite 2012.2


  • several bugfixes
  • new license format

HDL-Designer 2012.1 has been released


This bugfix release is available for download now.

UVM 1.1b


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