Welcome to the HES-SO Valais Wallis Wiki of the Infotronics Unit
This is the knowledge database of the HES-SO Valais Wallis Institute of Systems Engineering
Infotronics Unit. It's the place to share experiences, findings, how-to's and everything else about HDL, Telecom, Embedded Systems and related topics.
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- System Generator for DSP updates
- HLS imporvements
- further Device Support for Virtex-7, Artix-7 and Zynq-7000
Xilinx ISE 14.4 and Xilinx Vivado Design Suite 2012.4 introducing the Vivado WebPACK Tool have been released
- Performance and GUI improvements
- further VHDL-2008 support and inclusion of VHLD-2008 OSVVM librarires
- new SystemVerilog 1800-2012 support
Model-/QuestaSim 10.2 has been released
The presentation slides can be downloaded here.
After 7 years of development, Qt 5.0, centered around Qt Quick with the full capabilities of OpenGL/OpenGL ES, has been released.
- 5K - 120K LUTs, 190k - 4.5Mbit RAM, 11 -240 Math (DSP) blocks
- 166 MHz ARM® Cortex™-M3 microprocessor with 8Kbyte Instruction Cache
- connects to USB 2.0 HS OTG, CAN, SPI, I2C and Gigabit Ethernet
- static power 10mW during operation on the 50K LUT device
- 0 - 16 5Gbps SERDES, PCIe, XAUI / XGXS+ Native SERDES
- Hard 800 mbps DDR2/3 controllers with SECDED (aka ECC or EDAC) protection
- but no more DAC/ADC
- samples available now, first production silicon slated for early 2013
- Xilinx Vivado PAR support
- new Timing Report View
- compiler enhancements (SV, VHDL2008, ...)
- several bugfixes
- new license format
HDL-Designer 2012.1 has been released
This bugfix release is available for download now.