Welcome to the HES-SO Valais Wallis Wiki of the Infotronics Unit
This is the knowledge database of the HES-SO Valais Wallis Institute of Systems Engineering
Infotronics Unit. It's the place to share experiences, findings, how-to's and everything else about HDL, Telecom, Embedded Systems and related topics.
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Use the Navigation to the left to enter the different sections or follow any of the following links:
- Design Checker / Version Management / Register Assistant / Vendor Tool Support updates
- around 70 bugfixes!
- Many performance improvements
- New compact library format; WLF, GUI performance improvements
- Wave window undo/redo and cursor and time navigation improvements
- VHDL 2008 support improvements; Inclusion of VHDL-2008 OSVVM libraries
- IP updates
- further Device Support for Zynq-7000 and Defenense-Grade Zynq-7000Q, Artix-7Q, Virtex-7Q
- Extra editor windows: Window -> Open in New Window or Split -> Open in New Window (very useful for us dual-screeners)
- Progress information moved to the bottom-right corner (IMHO not really an improvement :( )
- Specific Python editor (highlighting, indentation and a python class wizard)
- More C++ refactoring actions
- Many new Git features
Like the old IGLOOs, it's based on the non-volatile Flash technology, with it's advantages of independence from external configuration devices, lower power (flash freeze), higher radiation immunity and security. Up until now, Flash based devices have been rather small. But with IGLOO2, Microsemi is now in direct competition with the other important FPGA manufacturers. IGLOO2 has
- 6-150 kLUTs (like Xilinx Artix-7 or Spartan6)
- up to 16 5G SerDes (competitors: <10)
- max. 574 User IOs (like Spartan6, more than Artix-7)
- 700-5000 kBits RAM
- up to 2 DDR controllers and 4 PCIe endpoints
The M2GL050 is already shipping and starts at less than $7USD for high volume orders.
- plugin updates (Spyder 2.2.0, Numpy, Scipy, PyQt ...)
- a dozen new plugins
- improved image manupulation
- adds large vector randomization
- has a work around for some Aldec issues
- Supported Families: SmartFusion2, SmartFusion, Fusion, ProASIC3, ProASIC3E, ProASIC3L, IGLOO, IGLOOe, IGLOO+
This update brings following new features to the 10.0 release:
- Improved GUI performance – Improved structure window and objects window
- VHDL Improvements - Support for significant portions of VHDL 2008 and Preservation
of user case in identifiers
- New advanced debug features including schematic view debug and automatic causality
- Improved WLF debugging and new Code Coverage Analysis Pane
- Improved Altera and Xilinx Vivado support
- New Microsemi SmartFusion2 Device
- Expanded SystemVerilog Support
- Improved Physical Plus for Xilinx devices
The IEEE Std 1800-2012 a.k.a. SystemVerilog is available for download
The 31 new features, 60 clarifications and 71 corrections of the standard include:
- Multiple inheritance !
- Soft constraints
- Uniqueness constraints
- A different global clock can be defined for each hierarchy scope
More infos here
The presentation slides can be downloaded here.
This bugfix release is available for download now.