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Welcome to the HES-SO Valais Wallis Wiki of the Infotronics Unit

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This is the knowledge database of the HES-SO Valais Wallis Institute of Systems Engineering Infotronics Unit. It's the place to share experiences, findings, how-to's and everything else about HDL, Telecom, Embedded Systems and related topics.

Find more information about our educational program in the FSI Wiki.

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Getting started

Use the Navigation to the left to enter the different sections or follow any of the following links:

News

2014-04-25

Model-/QuestaSim 10.3a is now available on guo's Software Server

  • Performance improvements
  • Beta of New Toolbars to improve GUI real estate
  • more VHDL 2008 support (if/cas/generate)
  • Support for Windows 8

Synplify 2014.3 is now available on guo's Software Server

  • QoR improvements
  • Asymmetric RAM enhancements
  • DSP enhancements
  • includes syntax help for VHDL constructs

2014-03-18

Xilinx ISE 14.7 is now available on guo's Software Server

IMPORTANT: As ISE enters it's sustaining phase of product life there will be no more major releases. However, updates and patches might still be released.

  • 7 series and Zynq device and IP updates

2011-01-07

HDL-Designer 2013.1 is now available on guo's Software Server

  • VHDL 2008: Logical Shift Operators, Simplified Case Statements, Delimited Comments
  • new SystemVerilog Assistant
  • Register Assistant 4.5, Design Checking Enhancements, Vendor flow updates, Platform support updates

2013-12-11

New Heavyweight FPGA Champion: Xilinx announced the new Virtex UltraScale All Programmable devices

This 3D IC contains three die (SLR) to achieve:

  • 4.4M logic cells (approx. 50M ASIC gates)
  • 88.6 Mbits BRAM
  • 2880 DSP48 slices (4268 GMACs/sec)
  • hard-IPs: 6 x PCIe, 3 x 100G Ethernet MAC, 48 x 16.3 Gbps transceivers
  • 1456 I/O Pins

2013-11-29

In need of a Qt Library? Like to publish one? Check out #inqlude!

Inqlude is meant to be the place where you find all information and pointers to Qt libraries, components or modules. There's the webpage, a format for describing Q-based libraries and a command line client to install libraries. It's all still in alpha phase, but certainly worth a look. For more and up-to-date information follow this link.

2013-07-18

Xilinx ISE 14.6 is now available on guo's Software Server

  • IP updates
  • further Device Support for Zynq-7000 and Defenense-Grade Zynq-7000Q, Artix-7Q, Virtex-7Q

2013-07-15

Qt Creator 2.8.0 has been released

  • Extra editor windows: Window -> Open in New Window or Split -> Open in New Window (very useful for us dual-screeners)
  • Progress information moved to the bottom-right corner (IMHO not really an improvement :( )
  • Specific Python editor (highlighting, indentation and a python class wizard)
  • More C++ refactoring actions
  • Many new Git features

2013-06-19

IGLOO for the masses: Microsemi announced the new IGLOO2 FPGA

Like the old IGLOOs, it's based on the non-volatile Flash technology, with it's advantages of independence from external configuration devices, lower power (flash freeze), higher radiation immunity and security. Up until now, Flash based devices have been rather small. But with IGLOO2, Microsemi is now in direct competition with the other important FPGA manufacturers. IGLOO2 has

  • 6-150 kLUTs (like Xilinx Artix-7 or Spartan6)
  • up to 16 5G SerDes (competitors: <10)
  • max. 574 User IOs (like Spartan6, more than Artix-7)
  • 700-5000 kBits RAM
  • up to 2 DDR controllers and 4 PCIe endpoints

The M2GL050 is already shipping and starts at less than $7USD for high volume orders.

2013-06-11

Python(x,y) 2.7.5.0 is now available on guo's Software Server

  • plugin updates (Spyder 2.2.0, Numpy, Scipy, PyQt ...)
  • a dozen new plugins
  • improved image manupulation

2013-05-31

OSVVM release 2013.05 is now available on guo's Software Server

  • adds large vector randomization
  • has a work around for some Aldec issues

2013-05-27

Microsemi Libero SoC 11.0 is now available on guo's Software Server

  • Supported Families: SmartFusion2, SmartFusion, Fusion, ProASIC3, ProASIC3E, ProASIC3L, IGLOO, IGLOOe, IGLOO+

Model-/QuestaSim 10.0f is now available on guo's Software Server

This update brings following new features to the 10.0 release:

  • Improved GUI performance – Improved structure window and objects window
  • VHDL Improvements - Support for significant portions of VHDL 2008 and Preservation

of user case in identifiers

  • New advanced debug features including schematic view debug and automatic causality

tracing

  • Improved WLF debugging and new Code Coverage Analysis Pane

The IEEE Std 1800-2012 a.k.a. SystemVerilog is available for download

The 31 new features, 60 clarifications and 71 corrections of the standard include:

  • Multiple inheritance !
  • Soft constraints
  • Uniqueness constraints
  • A different global clock can be defined for each hierarchy scope

More infos here

UIT Wiki Presentation

The presentation slides can be downloaded here.

UVM 1.1b

This bugfix release is available for download now.

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