Welcome to the HES-SO Valais Wallis Wiki of the Infotronics Unit
This is the knowledge database of the HES-SO Valais Wallis
Institute of Systems Engineering Infotronics Unit (UIT).
It's the place to share experiences, findings, how-to's and everything else about HDL, Telecom, Embedded Systems and related topics.
Find more information about our educational program in the FSI Wiki.
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Use the Navigation to the left to enter the different sections or follow any of the following links:
Top Programming Languages 2016 according to IEEE Spectrum
The GroupFPGA has been founded to bring together all the collaborators at HEI instersted in programmable logic.
The first meeting was accompanied by a presentation of the SpinalHDL by its inventor Charles Papon. A workshop about this language is planned in the near future.
The Raspberry Pi 3 finally has built-in 802.11n Wi-Fi and Bluetooth 4.0 (and BLE) and still only costs 35$. In comparison to the Raspberry Pi 2, the processor is about 50% faster with the 64-bit, 1.2 GHz ARM Cortex A53 and the graphics chips' speed is increased to 400 MHz. On the other side, the maximal current consumption is increased to 2.5 A.
The Modeling-Editor is still an early version, therefore it has to be activated in Help -> Plugin -> ModelEditor but it supports already Package, Class, Component, Use case and Activity diagrams. Elements can be added to the graphical view not only from the toolbar or the elements tree, but also by dropping source files on it.
HyperCam hyperspectral camera
Microsoft Research and the Universitiy of Washington just released a paper describing a camera that takes pictures at 17 different wavelengths.
SpinalHDL introduction in complex HDL projects
SpinalHDL, a very new high level hardware description library, is now used on the HDL complex design xADDACore - a fully auto-generated and customizable architecture for wide-band impedance spectroscopy (compatible with multiple hardware, some targeted projects : HiSADDA, IGOR V, MiniBioDet and OLGM).
More details on :
- VHDL 2008 enhancements
- SystemVerilog Assistant
- Xilinx Vivado interface
- bugfixes and minor enhancements
- Performance improvements for SV (OVM/UVM), VHDL, HTML and libraries
- New Toolbars (Edit Preferences)
- discontinued support for Windows XP and Vista!
- Compiler Enhancements
- new packages: numpy, jsonschema, mistune, ...
- upgraded many packages
- Enlarged support for SmartFusion2 and IGLOO2 families
- Runtime and UI improvements
- SoftConsole v3.4 requires the SP1 to be compatible with Libero SoC v11.4
IMPORTANT: As ISE enters it's sustaining phase of product life there will be no more major releases. However, updates and patches might still be released.
- 7 series and Zynq device and IP updates
New Heavyweight FPGA Champion: Xilinx announced the new Virtex UltraScale All Programmable devices
This 3D IC contains three die (SLR) to achieve:
- 4.4M logic cells (approx. 50M ASIC gates)
- 88.6 Mbits BRAM
- 2880 DSP48 slices (4268 GMACs/sec)
- hard-IPs: 6 x PCIe, 3 x 100G Ethernet MAC, 48 x 16.3 Gbps transceivers
- 1456 I/O Pins
In need of a Qt Library? Like to publish one? Check out #inqlude!
Inqlude is meant to be the place where you find all information and pointers to Qt libraries, components or modules. There's the webpage, a format for describing Q-based libraries and a command line client to install libraries. It's all still in alpha phase, but certainly worth a look. For more and up-to-date information follow this link.
- IP updates
- further Device Support for Zynq-7000 and Defenense-Grade Zynq-7000Q, Artix-7Q, Virtex-7Q
Like the old IGLOOs, it's based on the non-volatile Flash technology, with it's advantages of independence from external configuration devices, lower power (flash freeze), higher radiation immunity and security. Up until now, Flash based devices have been rather small. But with IGLOO2, Microsemi is now in direct competition with the other important FPGA manufacturers. IGLOO2 has
- 6-150 kLUTs (like Xilinx Artix-7 or Spartan6)
- up to 16 5G SerDes (competitors: <10)
- max. 574 User IOs (like Spartan6, more than Artix-7)
- 700-5000 kBits RAM
- up to 2 DDR controllers and 4 PCIe endpoints
The M2GL050 is already shipping and starts at less than $7USD for high volume orders.
- adds large vector randomization
- has a work around for some Aldec issues
The IEEE Std 1800-2012 a.k.a. SystemVerilog is available for download
The 31 new features, 60 clarifications and 71 corrections of the standard include:
- Multiple inheritance !
- Soft constraints
- Uniqueness constraints
- A different global clock can be defined for each hierarchy scope
More infos here
The presentation slides can be downloaded here.
This bugfix release is available for download now.