Projects
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== Math2Mat == | == Math2Mat == | ||
Automatically translate mathematical formulas to VHLD code, inclusive optimisation and testbench in SystemVerilog. | Automatically translate mathematical formulas to VHLD code, inclusive optimisation and testbench in SystemVerilog. | ||
| + | * [http://www.math2mat.ch/ Website] | ||
* [http://wiki.lii.eig.ch/wiki-math2mat/index.php/Accueil Wiki (login needed)] | * [http://wiki.lii.eig.ch/wiki-math2mat/index.php/Accueil Wiki (login needed)] | ||
* [https://svn.lii.eig.ch/trac/math2mat/wiki Trac] | * [https://svn.lii.eig.ch/trac/math2mat/wiki Trac] | ||
[[Category:Projects]] | [[Category:Projects]] | ||
Revision as of 15:13, 23 February 2012
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Here you can find a list of EDA projects carried out at the HES-SO//VS
USBCypress
This is a VHDL IP core which allows to connect a FPGA to PC over USB with help of a Cypress USB driver chip
AMBAdraw (a.k.a. AMBArchitect)
Graphical user interface (GUI) for GRLIB-AMBA
Math2Mat
Automatically translate mathematical formulas to VHLD code, inclusive optimisation and testbench in SystemVerilog.
