Projects/CubeCluster

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This is the public page of the CubeCluster project.
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=== CubeCluster Project ===
 
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[[File:Intel_edison_reduced.png|200px|thumb|Intel Edison System|right]]
CubeCluster is a development project for the pico-satellite CubeSat. It is an low-power high-performance processing board unit for such of CubeSat, allowinga high data treatment and low power consumption.
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[[File:Igloo.png|200px|thumb|Igloo FPGA|right]]
 
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CubeCluster is a development project part for the pico-satellite CubeSat. It is an low-power high-performance image processing board unit for CubeSat, allowing a high speed data treatment and low power consumption.
The CubeCluster unit deals with a multiprocessor architecture based on the Intel Edison SoC which reduces the consumption significally. On the the second hand an FPGA acts as the master device onboard for the data acquisition, data IO routing. The FPGA enables scheduling of the data treatements which are parallelized on each Intel Edison SoC.
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The CubeCluster unit deals with a multiprocessor architecture based on Intel Edison SoCs which can reduce the consumption significally. On the the second hand, a FPGA acts as master device onboard for the data acquisition and data IO routing. The FPGA focuses on scheduling of the data treatements which are parallelized on each Intel Edison SoC.
  
 
= Further Infos =
 
= Further Infos =
[[Projects/CubeCluster/Demonstrator|Demonstrator]]
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* [[Hardware/FPGARackEdison|Hardware]]
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* [[Projects/CubeCluster/Demonstrator|Demonstrator]]
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* [http://www.hevs.ch/fr/rad-instituts/institut-systemes-industriels/projets/low-power-high-performance-unit-for-cubesat-10440 Short presentation]

Latest revision as of 13:13, 8 August 2016

Contents

CubeCluster Project

Intel Edison System
Igloo FPGA

CubeCluster is a development project part for the pico-satellite CubeSat. It is an low-power high-performance image processing board unit for CubeSat, allowing a high speed data treatment and low power consumption. The CubeCluster unit deals with a multiprocessor architecture based on Intel Edison SoCs which can reduce the consumption significally. On the the second hand, a FPGA acts as master device onboard for the data acquisition and data IO routing. The FPGA focuses on scheduling of the data treatements which are parallelized on each Intel Edison SoC.

Further Infos

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