Projects/USLO

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The aim of the project is to demonstrate the feasibility of a cheap and miniature ophthalmoscope based on versatile and portable MEMS scanning mirrors, capable of three-dimensional measurements of different structures of the fundus, including the optic nerve head, and functional measures requiring excitation. Such a device could be acquired by ophthalmologists, but also by general practice or paramedical staff (orthoptists, nurses and opticians) for the systematic and remote screening of glaucoma. This page describes the electronic system. For details about the optical system see TBD.

System

The proposed electronic system contains three main parts:

  • a system controller
  • the mirror controller
  • the data acquisition

USLO Electronic System

The Controller forms the bridge between a processor system on one side and the electronic circuitry on the other side. The computer is used to analyze and visualize the collected data. The electronic circuitry transforms the signals from the digital domain into the analogue domain of the mirrors and also from analogue to digital for the image sensor.

Hardware

USLO FPGArack toplevel

Thanks to using existing hardware extensively we have been able to build a working prototype in a short time-frame.

System Controller

The System Controller is realized on a HEI FPGA-Rack FPGA board. This is a standard FPGA board used at UIT for various projects designed to fit in two rack units (2U). The controlling is implemented in the Xilinx Spartan-6 LX FPGA. The USB connector is used to send the collected data on to a computer. On the other side, the VME 96 pin connects to other electronic components used for signal transformation.

Mirror Controller

The mirrors' angle is proportional to a current of ±10 mA and ±15 mA and controlled by an FPGA. For this we use an DAC to transform the digital signal from the FPGA into a tension, and then a Howland Current Pump to transform the tension into current.

TBD: basic schematic

DAC

DAC Analogue Output Stage with Pull-Up Resistor
ADC-DAC board with soldered resistors for DAC DC-offset

The DAC in use is the PCM1793 24-BIT, 192kHz Stereo D/A converter on the HEI PP Audio ADC DAC board. This DAC was chosen, because it fulfils the requirements of this project and we had it ready to use on our PP Audio ADC DAC board. This board is designed for audio applications and therefore cancels out any DC-offset. We soldered a 6.4 kΩ pull-up resistor on the positive input of the OpAmp on the Analogue Output Stage. This resistor forms a voltage divider with the 3.3 kΩ resistor to halve the supply voltage.

V_{out} = - \frac{R_2}{R_1} (V_- - V_+) + \frac{R_2}{R_3} * V_{cc}

As we like to define the DC current, i.e. when there is no differential voltage applied:

VV + = 0.

Therefore we can simplify:

V_{out} = \frac{R_2}{R_3} * V_{cc}

And with this:

R_3 = R_2 *  \frac{V_{cc}}{V_{out}} = 3.3\ k\Omega * \frac{5\ V}{2.5\ V} = 6.6\ k\Omega

As it is a stereo Audio-DAC, it is furnished with 2 channels: left and right. In this application we use one channel per mirror.

Howland Current Pump

Howland Current Pump circuit

A Howloand Current Pump is used to convert the voltage signal from the DAC into a current signal for the mirrors. Thereby we use the "Improved Howland Current Pump" with trimmer (for more information please refer to AN-1515 A Comprehensive Study of the Howland Current Pump).

We did a simulation in P-Spice to better understand the circuit and to specify the resistors' values.

TBD: howland schematic and simulation

This functionality was then realized on a dedicated PCB with a phone connector for the input signals from the audio DAC and a D-sub connector towards the mirrors.

Data Acquisition

An Avalanche Photodiode (APD) module captures the light reflected by the eye. We used the File:C5460 series kacc1010e06.pdf. The output of this module varies between -10 V to 0 V. As the controlling FPGA works best with signals between 0 V and 5 V, a general inverting amplifying circuit (HEB_GIA) has been developed based on the PP board design. The resulting signal is digitized by the PCM1804 full differential analog input 24-BIT, 192-kHz stereo A/D converter on the HEI PP Audio ADC DAC board and send on to the controlling FPGA.

TBD: picture HEB_GIA

ISI toaster

USLO PP-Backplane with daughtercards
USLO ISI toaster fully equipped

To provide a compact and transportable system, we invented the ISI toaster containing a FPGA Rack Backplane Stack board. It allows to mount up to four rack cards in a 3D printed housing with a screwed on front panel. For USLO it holds a PP-Backplane board with all the small extension cards explained above mounted on, and an FPGArack board with the controlling FPGA.

Hardware Configuration

Also the hardware configuration on the controlling FPGArack FPGA is separated into two distinct parts, one to control the mirrors and the other one for data acquisition.

TBD: top-level block-diagram

Mirror Control

TBD: block-diagram

Data Acquisition

TBD: block-diagram


Synthesis Flow

HDL-Designer -> Synplify -> ISE


TBD

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