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The aim of the project is to demonstrate the feasibility of a cheap and miniature ophthalmoscope based on versatile and portable MEMS scanning mirrors, capable of three-dimensional measurements of different structures of the fundus, including the optic nerve head, and functional measures requiring excitation. Such a device could be acquired by ophthalmologists, but also by general practice or paramedical staff (orthoptists, nurses and opticians) for the systematic and remote screening of glaucoma. This page describes the electronic system. For details about the optical system see TBD. For details about the image processing system see TBD.


The proposed electronic system forms a bridge between the optical system with the mirrors and the sensor on one side and a processing system to visualize the captured image on the other side. It can be split into three separate parts:

  • a system controller
  • the mirror controller
  • the data acquisition
USLO Electronic System
USLO Electronic System Connectors

The System Controller links the processor system to the analogue electronic circuitry. It controls the angle of the mirrors and samples the collected data. The light data is packaged into images of 100 x 100 monochrome pixels and then sent on to the processor system.

The processor system is used to analyze and visualize the collected data. To be as flexible as possible it uses a USB connection.

The electronic circuitry transforms the signals from the digital domain into the analogue domain of the mirrors and also from analogue to digital for the image sensor. The image sensor is connected with an microfiber cable to the optical system. The mirrors use a 9-pin D-sub connector.

To power the system a power supply with ±5 Volt and ±12 Volt is needed.

In order to verify the functionality of the system, we wrote a little Python application. When it runs on the processor system, i.e. a computer with Windows, it generates image files from the data received over USB.

TBD upload app


Thanks to using existing hardware extensively we have been able to build a working prototype in a short time-frame.

System Controller

The System Controller is realized on a HEI FPGA-Rack FPGA board. This is a standard FPGA board used at the UIT for various projects designed to fit into two rack units (2U). The controlling is implemented in the Xilinx Spartan-6 LX FPGA. The VHDL design can be found on our svn repository.

USB connection

A USB connector, which acts as serial COM-port on the receiving end, is used to send the collected data on to the processor system. The low-level protocol is RS232 with 1 start bit and 8 data bits and a baud rate of TBD. The targeted bitrate was 3'000'000 bit/s. Test on a standard PC showed that at this speed, some data bits are not received (~5%). Therefore a version with a bitrate of 1'000'000 bit/s (1 Mbit/s) has been generated. Here all the bits are received correctly.


To transmit the images an image transfer protocol has been developed. The goal of this protocol is to be able to verify the good reception of an image on the processor system. It should also be able to show an image even if there are some pixels missing in a line. Therefore a marker for each image as well as each line have been introduced.

The RS232 splits the data into words of 8 bit. In our image transfer protocol, the most significant bit is always a control bit. It defines if the following seven bits of the word are control bits or bits of a pixel. There exist 3 different words with control data:

  • Start of Image (SoI): 0b10000001 = 0x81
  • End of Line (EoL): 0b10000011 = 0x83
  • End of Image (EoI): 0b10001010 = 0x8a

Two data words are used to transmit the luminance value of one pixel:

  • MSB (13:7): 0b0xxxxxxx
  • LSB ( 6:0): 0b0xxxxxxx

As a result, there are 14 data bits per pixel.

A shown in the graphic below, at the beginning of an image the SoI word is sent. Then follow all the 100 lines of the image. Each line of 100 image pixels and therefore 200 data words is terminated with the EoL word. The whole image is wrapped up with the EoI word.

USLO Image Transfer Protocol
SoI 10000001
Data + EoL 0xxxxxxx 0xxxxxxx 10000011
Data + EoL 0xxxxxxx 0xxxxxxx 10000011
EoI 10001010

This protocol adds some overhead, so that we have

(100 * 100 * 2) \frac{data words}{image} + (100 + 2) \frac{control words}{image} = 20102 \frac{words}{image}

For each word, there are

8databit + 1startbit + 1stopbit = 10bits

which have to be transmitted. This results in

20102 \frac{words}{image} * 10 \frac{bits}{word} = 201020 \frac{bits}{image}

So for one pixel we have

\frac{201020 \frac{bits}{image}}{10000 \frac{pixel}{image}} \approx 20\frac{bits}{pixel}

and therefore

20\frac{transmitted bits}{pixel}-14\frac{data bits}{pixel}=6\frac{overhead bits}{pixel}

To increase the transmission speed of this protocol, the EoI or even the EoL marker could be omitted. However the capacity to display images with missing pixels would be greatly reduced.

Image Rate

At the targeted bitrate of 3'000'000 bits/sec the maximal image rate is

\frac{3000000 \frac{bits}{sec}}{201020 \frac{bits}{image}} \approx 15 \frac{images}{sec}

and at the lower test bitrate of 1'000'000 bits/sec

\frac{1000000 \frac{bits}{sec} }{ 201020 \frac{bits}{image}} \approx 5 \frac{images}{sec}


On the other side, the VME 96-pin connector connects to other electronic components used for signal transformation. The pin assignment is based on the HEI VME Backplane Bus.

Mirror Controller

The mirrors' angle is proportional to a current of ±10 mA and ±15 mA and controlled by an FPGA. For this we use an DAC to transform the digital signal from the FPGA into a tension, and then a Howland Current Pump to transform the tension into current.

TBD: basic schematic


DAC Analogue Output Stage with Pull-Up Resistor
ADC-DAC board with soldered resistors for DAC DC-offset

The DAC in use is the PCM1793 24-BIT, 192kHz Stereo D/A converter on the HEI PP Audio ADC DAC board. This DAC was chosen, because it fulfils the requirements of this project and we had it ready to use on our PP Audio ADC DAC board. This board is designed for audio applications and therefore cancels out any DC-offset. We soldered a 6.4 kΩ pull-up resistor on the positive input of the OpAmp on the Analogue Output Stage. This resistor forms a voltage divider with the 3.3 kΩ resistor to halve the supply voltage.

V_{out} = - \frac{R_2}{R_1} (V_- - V_+) + \frac{R_2}{R_3} * V_{cc}

As we like to define the DC current, i.e. when there is no differential voltage applied:

VV + = 0.

Therefore we can simplify:

V_{out} = \frac{R_2}{R_3} * V_{cc}

And with this:

R_3 = R_2 *  \frac{V_{cc}}{V_{out}} = 3.3\ k\Omega * \frac{5\ V}{2.5\ V} = 6.6\ k\Omega

As it is a stereo Audio-DAC, it is furnished with 2 channels: left and right. In this application we use one channel per mirror.

Howland Current Pump

Howland Current Pump circuit

A Howloand Current Pump is used to convert the voltage signal from the DAC into a current signal for the mirrors. Thereby we use the "Improved Howland Current Pump" with trimmer (for more information please refer to AN-1515 A Comprehensive Study of the Howland Current Pump).

We did a simulation in P-Spice to better understand the circuit and to specify the resistors' values.

TBD: howland schematic and simulation

This functionality was then realized on a dedicated PCB with a phone connector for the input signals from the audio DAC and a D-sub connector towards the mirrors.

Data Acquisition

An Avalanche Photodiode (APD) module captures the light reflected by the eye. We used the Hamamatsu C5460 APD module. The output of this module varies between -10 V to 0 V. As the controlling FPGA works best with signals between 0 V and 5 V, a general inverting amplifying circuit (HEB_GIA) has been developed based on the PP board design. The resulting signal is digitized by the PCM1804 full differential analog input 24-BIT, 192-kHz stereo A/D converter on the HEI PP Audio ADC DAC board and sent on to the controlling FPGA.

TBD: picture HEB_GIA

ISI toaster

USLO PP-Backplane with daughtercards
USLO ISI toaster fully equipped

To provide a compact and transportable system, we invented the ISI toaster containing a FPGA Rack Backplane Stack board. It allows to mount up to four rack cards in a 3D printed housing with a screwed on front panel. For USLO it holds a PP-Backplane board with all the small extension cards explained above mounted on, and an FPGArack board with the controlling FPGA.

Hardware Configuration

USLO FPGArack toplevel

Also the hardware configuration on the controlling FPGArack FPGA is separated into two distinct parts, one to control the mirrors and the other one for data acquisition.

Mirror Control

Here we have four blocks, where there are simple counters and the fourth one controls the DAC.

The first counter block called Prescaler generates a pulse every time the mirrors can move to a new pixel location. We are able to modify the image rate by adjusting the frequency of this pulser. All the rest of the design is coupled to this pulser and therefor adapts automatically to any chosen image sampling frequency. If we like to fully use the speed of the serial link to the processor system of 1'000'000 bit/sec we get

(100*100) \frac{pixels}{image} * 5 \frac{images}{sec} = 50000 \frac{pixels}{sec}

To allow for some protocol overhead and to be able to implement an effective Prescaler, we settled for 42500 pixels/sec.

\frac{42500 \frac{pixels}{sec}}{(100*100)\frac{pixels}{image}} = 4.25 \frac{image}{sec}  \Rightarrow  0.235 \frac{sec}{img}

Together with the overhead of the protocol this leads to ultimately

4.25 \frac{images}{sec} * 201020 \frac{bits}{image} = 854335 \frac{bits}{sec}

To compensate some mechanical shortcommings of the mirrors, also a slower pixel rate of 425 pixel/sec has been tested:

\frac{425 \frac{bits}{sec}}{(100*100)\frac{pixels}{image}} = 0.0425 \frac{image}{sec}  \Rightarrow  23.5 \frac{sec}{img} \Rightarrow  2.35 \frac{msec}{pixel}

Together with the overhead of the protocol this gives

0.0425 \frac{images}{sec} * 201020 \frac{bits}{image} = 8543 \frac{bits}{sec}

Then FastMirrorCnt generates the controlling signal of the fast moving mirror. On every pulse from the Prescaler the counter increments by one. When it arrives at 100, it returns to 0 and sends a pulse to the next counter. So to speak it counts the pixel on each line, or in other words, it's the vertical counter.

The SlowMirrorCnt works exactly the same way as the FastMirrorCnt. It increments on each pulse from the FastMirrorCnt until 100 is reached. Then it restarts at 0 and sends out a pulse. This means it counts the lines on each image, or in other words, it's the horizontal counter.

ADCctrl interfaces with the ADC and sends the counter values from FastMirrorCnt and SlowMirrorCnt over a 24-bit I2S connection. There they are sampled at 192 kHz which equals to about

\frac{192000 \frac{samples}{sec}}{42500 \frac{pixels}{sec}} \approx 4.5 \frac{samples}{pixel}.

Data Acquisition

Here we also have four main blocks. The data flows from the DAC to the serial port. It is also received over a 24-bit I2S connection. The DACctrl puts it into a parallel format. As the DAC is primarily intended for audio applications, its sampling speed is per default 192 kHz.

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