Standards/Ethernet PTP/DP83640

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| enable mii || <code><span style="color:red">miim0 y</span></code>
 
| enable mii || <code><span style="color:red">miim0 y</span></code>
 
|-
 
|-
| read - phy no. - reg. no || <code><span style="color:red">rd 01 13</span></code>
+
| read - phy no. - reg. no || <code><span style="color:red">rd 0113</span></code>
 
|-  
 
|-  
| write - phy no. - reg. no - data || <code><span style="color:red">wr 01 13 0004</span></code>
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| write - phy no. - reg. no - data || <code><span style="color:red">wr 0113 0004</span></code>
 
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|-
 
|}
 
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! action !! command !! response
 
! action !! command !! response
 
|-
 
|-
| Select Page 4 || <code><span style="color:red">wr 01 13 0004</span></code>
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| Select Page 4 || <code><span style="color:red">wr 0113 0004</span></code>
 
|-  
 
|-  
| Read selected page || <code><span style="color:red">rd 01 13</span></code> || <code><span style="color:blue">0004</span></code>
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| Read selected page || <code><span style="color:red">rd 0113</span></code> || <code><span style="color:blue">0004</span></code>
 
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Revision as of 10:06, 16 June 2014

Contents

The National Semiconductor DP83640 Precision PHYTER is an ethernet transceiver that integrates certain features useful for the implementation of the IEEE 1588 standard. The three main features are:

  • packet time stamping
  • synchronised clock generation \tfrac{250MHz}{n=2\ldots255} (PTP_COC and PTP_RATE register)
  • event triggering and time stamping with GPIOs

other technical features include:

  • IEEE 1588 V1 and V2 support
  • Timestamp resolution of 8 ns (Allows sub 10 ns synchronization to master reference)
  • Error-free Operation up to 150 meters CAT5 cable

IEEE 1588

Paket Timestamp

TX

Outgoing IEEE 1588 V1 and V2 Event messages are detected automatically and a timestamp is recorded. For the two-step mode an interrupt can be generated when a timestamp is ready to be read by the PHYTER controller. For the one-step mode the transmitter can also be configured to insert the timestamp directly into Sync messages.

RX

Incoming IEEE 1588 V1 and V2 Event messages are detected automatically and a timestamp is recorded. An interrupt is generated an the timestamp can be read by the PHYTER controller. The timestamp can also be integrated into the received packet for easy transmission to the PHYTER controller.

Event

Output Trigger

A trigger signal based on the IEEE 1588 time value can be put out a desired GPIO. The triggers can generate:

  • one-time rising or falling edge
  • single pulse with a configurable with
  • periodic signal

The device supports up to 8 triggers. They can be put out on single GPIOs or be OR'ed together on single GPIOs.

Input Timestamp

The Event Timestamp Unit can monitor up to 8 events of:

  • rising edge
  • falling edge
  • both

assigned to any of the GPIOs. Event timestamps should be adjusted by 35 ns to compensate for internal delays.

MII

PHY address

The PHY address can be configured with 5 pins. The default setting is 00001. With all bits tied to 0 the PHY enters Isolation Mode where it disables parts of the MII interface.

Broadcast mode

The device is configured to accept broadcast messages by setting a register bit (PHY_CR2: BC_WRITE).

Registers

There are 20 fixed registers (0x00 ... 0x13) and 7 pages with 12 registers (0x14 ... 0x1F) each. In the fixed register PAGESEL (address: 0x13) field PAGE_SEL (bits: 2:0) selects the page to access. The pages are:

Page 0 
Extended Registers
Page 1
Test Registers - Reserved
Page 2
Link Diagnostics Registers
Page 3
Reserved Registers - Reserved
Page 4
PTP 1588 Base Registers
Page 5
PTP 1588 Configuration Registers
Page 6
PTP 1588 Configuration Registers

RS232 access

The baud rate configured in PTP is 19'200.

Base access

RS232 base access
action command
enable mii miim0 y
read - phy no. - reg. no rd 0113
write - phy no. - reg. no - data wr 0113 0004

Select page

RS232 select page
action command response
Select Page 4 wr 0113 0004
Read selected page rd 0113 0004

Init phyter

RS232 select page
action command
Select Page 4 wr 0113 0004
Enable Clock wr 0114 0004
Select Page 5 wr 0113 0005
Configure TX:
  • SYNC_1STEP
  • DR_INSERT
  • IGNORE_2STEP
  • CRC_1STEP
  • CHK_1STEP
  • TX_L2_EN
  • TX_IPV4_EN
  • TX_PTP_VER
  • TX_TS_EN
wr 01 16 AEA5

Time

Set
RS232 set time
action command
Select Page 4 wr 01 13 0004
Write Clock_time_ns[15:0] to PTP_TDR wr 0115 0000
Write Clock_time_ns[31:16] to PTP_TDR wr 0115 0000
Write Clock_time_sec[15:0] to PTP_TDR wr 0115 0000
Write Clock_time_sec[31:16] to PTP_TDR wr 0115 0000
Write to PTP_CTL with the PTP_Load_Clk bit set wr 0114 0010
Read
RS232 read time
action command response
Select Page 4 wr 01 13 0004
Write to PTP_CTL with the PTP_Rd_Clk bit set TBD
Read Clock_time_ns[15:0] from PTP_TDR rd 0115 4878
Read Clock_time_ns[31:16] from PTP_TDR rd 0115 055D
Read Clock_time_sec[15:0] from PTP_TDR rd 0115 0DFF
Read Clock_time_sec[31:16] from PTP_TDR rd 0115 0000

Event

RS232 timestamp GPIO
action command
Select Page 5 wr 01 13 0005
Config PTP_EVNT:
  • EVNT_RISE
  • EVNT_GPIO 1
  • EVNT_SEL 1
  • EVNT_WR 1

"0100_0001_0000_0011"

wr 01 15 4103

References

  1. Datasheet
  2. Product Page
  3. Press Release
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