Talk:Standards/HEI 'VME' Backplane Bus
(Difference between revisions)
Line 1: | Line 1: | ||
− | * Write error indication to master | + | * VME - Critical : Write error indication to master (latency implications...) |
− | * Ethernet communication TTP or Adele register based | + | * VME - Critical : Wait cycles... or not ? |
− | * Fix bug Ethernet (RAM full, CRC error) | + | * VME - Note : Data parity -> Hamming |
− | * RAM - FIFO thing | + | * ETH - Note : Ethernet communication TTP or Adele register based |
− | + | * ETH - Critical : : Fix bug Ethernet (RAM full, CRC error) | |
+ | * ETH - Note : RAM - FIFO thing |
Revision as of 10:58, 28 March 2013
- VME - Critical : Write error indication to master (latency implications...)
- VME - Critical : Wait cycles... or not ?
- VME - Note : Data parity -> Hamming
- ETH - Note : Ethernet communication TTP or Adele register based
- ETH - Critical : : Fix bug Ethernet (RAM full, CRC error)
- ETH - Note : RAM - FIFO thing