Talk:Standards/HEI 'VME' Backplane Bus

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* Write error indication to master
+
* VME - Critical : Write error indication to master (latency implications...)
* Ethernet communication TTP or Adele register based
+
* VME - Critical : Wait cycles... or not ?
* Fix bug Ethernet (RAM full, CRC error)
+
* VME - Note : Data parity -> Hamming
* RAM - FIFO thing
+
* ETH - Note : Ethernet communication TTP or Adele register based
*
+
* ETH - Critical :  : Fix bug Ethernet (RAM full, CRC error)
 +
* ETH - Note : RAM - FIFO thing

Revision as of 10:58, 28 March 2013

  • VME - Critical : Write error indication to master (latency implications...)
  • VME - Critical : Wait cycles... or not ?
  • VME - Note : Data parity -> Hamming
  • ETH - Note : Ethernet communication TTP or Adele register based
  • ETH - Critical :  : Fix bug Ethernet (RAM full, CRC error)
  • ETH - Note : RAM - FIFO thing
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